Clock and data recovery of sub-rate data

Patent metadata

Field	Value
Publication number	US-10396803-B2
Application number	US-201816165577-A
Country	US
Kind code	B2
Filing date	Oct 19, 2018
Priority date	Jan 10, 2018
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.

First claim

What is claimed is:

1. A clock and data recovery (CDR) circuit comprising:
a phase detector configured to detect phase of a data input signal based on a first clock pair and a second clock pair;
a controller configured to adjust a phase of the first clock pair, based on an output of the phase detector, to align an edge of the first clock pair to an edge of the data input signal, the controller further configured to:
1) in a first mode, adjust a phase of the second clock pair, based on an output of the phase detector, to align an edge of the second clock signal to a quadrature phase of the data input signal; and
2) in a second mode corresponding to the data signal being a sub-rate data signal, shift a first clock of the second clock pair toward a quadrature phase of the data signal; and

a masking circuit configured to selectively mask data bits clocked by a second clock of the second clock pair based on an indication of the first and second mode.

2. The circuit of claim 1 , wherein the masking circuit is further configured to selectively mask the data bits by outputting data bits clocked by the first clock of the second clock pair in place of the data bits clocked by the second clock of the second clock pair.

3. The circuit of claim 1 , wherein the masking circuit is further configured to selectively mask the data bits by outputting no data bit in place of the data bits.

4. The circuit of claim 1 , wherein the masking circuit is further configured to selectively mask data bits clocked by one clock of the first clock pair.

5. The circuit of claim 4 , wherein the masking circuit is further configured to selectively mask the data bits clocked by the one clock of the first clock pair by outputting data bits clocked by the other clock of the first clock pair in place of the data bits clocked by the one clock of the first clock pair.

6. The circuit of claim 4 , wherein the masking circuit is further configured to selectively mask the data bits clocked by the one clock of the first clock pair by outputting no data bit in place of the data bits clocked by the one clock of the first clock pair.

7. The circuit of claim 1 , further including a deserializer configured to deserialize the data input signal based on the first and second clock pairs and output the data bits.

8. The circuit of claim 1 , further comprising a charge pump configured to generate a control voltage based on an output of the phase detector, the controller further configured to adjust the phase of the first and second clock pairs based on the control voltage.

9. The circuit of claim 1 , wherein the controller includes a delay-locked loop (DLL) configured to generate the first and second clock pairs based on a reference clock signal.

10. The circuit of claim 1 , wherein the sub-rate data signal has a frequency that is a division by 2 n of a frequency of the first and second clock pairs, where n is a positive integer.

11. A method comprising:
detecting a phase of a data input signal based on a first clock pair and a second clock pair;
adjusting a phase of the first clock pair, based on the detected phase, to align an edge of the first clock pair to an edge of the data input signal;
in a first mode, adjusting a phase of the second clock pair, based on the detected phase, to align an edge of the second clock signal to a quadrature phase of the data input signal;
in a second mode corresponding to the data signal being a sub-rate data signal, shifting a first clock of the second clock pair toward a quadrature phase of the data signal; and
selectively masking data bits clocked by a second clock of the second clock pair based on an indication of the first and second mode.

12. The method of claim 11 , further comprising selectively masking the data bits by outputting data bits clocked by the first clock of the second clock pair in place of the data bits clocked by the second clock of the second clock pair.

13. The method of claim 11 , further comprising selectively masking the data bits by outputting no data bit in place of the data bits.

14. The method of claim 11 , further comprising selectively masking data bits clocked by one clock of the first clock pair.

15. The method of claim 14 , further comprising selectively masking the data bits clocked by the one clock of the first clock pair by outputting data bits clocked by the other clock of the first clock pair in place of the data bits clocked by the one clock of the first clock pair.

16. The method of claim 14 , further comprising selectively masking the data bits clocked by the one clock of the first clock pair by outputting no data bit in place of the data bits clocked by the one clock of the first clock pair.

17. The method of claim 11 , further comprising deserializing the data input signal based on the first and second clock pairs and outputting the data bits as a function of the deserializing.

18. The method of claim 11 , further comprising generating a control voltage based on an output of the phase detector and adjusting the phase of the first and second clock pairs based on the control voltage.

19. The method of claim 11 , further comprising controlling a delay-locked loop (DLL) to generate the first and second clock pairs based on a reference clock signal.

20. The method of claim 11 , wherein the sub-rate data signal has a frequency that is a division by 2*n of a frequency of the first and second clock pairs, where n is a positive integer.

Assignees

• Marvell Int Ltd

Inventors

• Meninger Scott E
• Crain Ethan
• Spaeth Mark

Classifications

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title