Qubit network non-volatile identification

Patent metadata

Field	Value
Publication number	US-10396268-B2
Application number	US-201715813247-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	May 18, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

First claim

What is claimed is:

1. A method of forming a superconducting chip comprising:
providing resonant units having resonant frequencies, Josephson junctions being in the resonant units;
causing one or more of the Josephson junctions to have a shorted tunnel barrier; and
causing one or more of the Josephson junctions to have no shorted tunnel barrier, wherein the resonant frequencies are designed to fall within a frequency band for each of the resonant units having the no shorted tunnel barrier in the Josephson junctions.

2. The method of claim 1 , wherein the shorted tunnel barrier causes an increase in the resonant frequencies for the resonant units having the shorted tunnel barrier.

3. The method of claim 1 , wherein some of the Josephson junctions have a tunnel barrier that is not shorted.

4. The method of claim 1 , wherein the resonant frequencies for the resonant units having the shorted tunnel barrier are designed to fall outside of the frequency band.

5. The method of claim 1 , wherein the Josephson junctions having the shorted tunnel barrier are determined in order to define a chip identification.

6. The method of claim 1 , wherein:
the Josephson junctions are structured to have a first configuration or a second configuration;
the first configuration is a non-shorted Josephson junction, the non-shorted Josephson junction having a tunnel barrier defined as not being shorted; and
the second configuration is a shorted Josephson junction, the shorted Josephson junction being defined as having the shorted tunnel barrier.

7. The method of claim 6 , wherein a combination of the first configuration and the second configuration defines a binary representation.

8. The method of claim 6 , wherein a combination of the resonant frequencies, associated with the first configuration and the second configuration, defines a binary representation.

9. The method of claim 1 , wherein:
the resonant units having the Josephson junctions without the shorted tunnel barrier are configured to be read out as a first binary number; and
the resonant units having the one or more of the Josephson junctions with the shorted tunnel barrier are configured to be read out as a second binary number.

Assignees

• IBM

Inventors

• Brink Markus
• Hertzberg Jared B
• Rosenblatt Sami

Classifications

• H10W46/407

  for wireless electrical read out · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C11/44

  using super-conductive elements, e.g. cryotron · CPC title