Semiconductor device

Patent metadata

Field	Value
Publication number	US-10396008-B2
Application number	US-201715855210-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Jan 27, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A semiconductor device includes a first metal plate and a second metal plate which interpose a first semiconductor element therebetween, the first metal plate and the second metal plate being bonded to the first semiconductor element with first soldered portions; and includes a third metal plate and a fourth metal plate which interpose a second semiconductor element therebetween, the third metal plate and the fourth metal plate being bonded to the second semiconductor element with second soldered portions. A first joint provided at an edge of the first metal plate and a second joint provided at an edge of the fourth metal plate are bonded with a third soldered portion. A total sum of thicknesses of the first soldered portions is different from a thickness of the third soldered portion, a solidifying point of the thinner one is higher than a solidifying point of the thicker one.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element comprising electrodes on both surfaces thereof;
a first metal plate and a second metal plate which interpose the first semiconductor element therebetween, the first metal plate and the second metal plate respectively being bonded to the electrodes of the first semiconductor element with respective first soldered portions;
a third metal plate and a fourth metal plate which interpose the second semiconductor element therebetween, the third metal plate and the fourth metal plate respectively being bonded to the electrodes of the second semiconductor element with respective second soldered portions; and
a resin package in which the first semiconductor element and the second semiconductor element are embedded, the first metal plate and the third metal plate being exposed at one surface of the resin package, and the second metal plate and the fourth metal plate being exposed at an opposite surface to the one surface of the resin package,
wherein
a first joint is provided at an edge of the first metal plate,
a second joint is provided at an edge of the fourth metal plate,
the first joint overlaps with the second joint as seen along a direction in which the first metal plate and the first semiconductor element are stacked,
the first joint and the second joint are bonded with a third soldered portion,
a total sum of thicknesses of the first soldered portions between the first metal plate and the second metal plate is different from a thickness of the third soldered portion between the first joint and the second joint, a solidifying point of a thinner one of the first soldered portions and the third soldered portion is higher than a solidifying point of a thicker one of the first soldered portions and the third soldered portion, and
a total sum of thicknesses of the second soldered portions between the third metal plate and the fourth metal plate is different from the thickness of the third soldered portion between the first joint and the second joint, a solidifying point of a thinner one of the second soldered portions and the third soldered portion is higher than a solidifying point of a thicker one of the second soldered portions and the third soldered portion.

2. The semiconductor device as in claim 1 , wherein
the total sum of the thicknesses of the first soldered portions is thinner than the thickness of the third soldered portion, and
the total sum of the thicknesses of the second soldered portions is thinner than the thickness of the third soldered portion.

Assignees

• Toyota Motor Co Ltd

Inventors

• Takahagi Satoshi
• Kadoguchi Takuya
• Hanaki Yuji
• Funano Syou
• Iwasaki Shingo
• Kawashima Takanori

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W76/138

  having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type · CPC title

• H10W74/111 Primary

  the semiconductor body being completely enclosed · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title