Electronic device

Patent metadata

Field	Value
Publication number	US-10395708-B2
Application number	US-201816055624-A
Country	US
Kind code	B2
Filing date	Aug 6, 2018
Priority date	Sep 7, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the free layer includes:
a first sublayer having a damping constant of 0.1 or less;
a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×10 4 to 1.0×10 8 erg/cm 3 ; and
an insertion layer interposed between the first sublayer and the second sublayer.

2. The electronic device of claim 1 , wherein the second sublayer is disposed closer to the tunnel barrier layer than the first sublayer is.

3. The electronic device of claim 1 , wherein the first sublayer includes a Heusler alloy, a half-Heusler alloy, or a half-metal, or a combination thereof.

4. The electronic device of claim 1 , wherein the insertion layer includes a material blocking crystallinity that is transferred from a layer disposed below the insertion layer.

5. The electronic device of claim 4 , wherein the insertion layer includes Zr, Hf, V, Cr, Cu, Nb, Mo, Ru, Rh, Ta, W, Re or Ir, or a combination thereof.

6. The electronic device of claim 1 , wherein the second sublayer includes an alloy or a stack structure, which includes Co, Fe or B, or a combination thereof.

7. The electronic device of claim 6 , wherein the second sublayer includes a Co—Fe—B alloy or a Co—Fe—B—X alloy (where X may be Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, W or Pt).

8. The electronic device of claim 1 , wherein the first sublayer has a damping constant ranging from 0.001 to 0.1.

9. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

10. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

11. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

12. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

13. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

14. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes a variable resistance element,
wherein the variable resistance element includes:
a free layer having a variable magnetization direction;
a pinned layer having a fixed magnetization direction; and
a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the free layer includes:
a first sublayer including a Heusler alloy, a half-Heusler alloy, or a half-metal, or a combination thereof;
a second sublayer including an alloy or a stack structure which includes Co, Fe or B, or a combination thereof; and
an insertion layer interposed between the first sublayer and the second sublayer.

15. The electronic device of claim 14 , wherein the first sublayer is structured to decrease a damping constant of the free layer.

16. The electronic device of claim 14 , wherein the second sublayer is structured to maintain a perpendicular magnetic anisotropy energy density of the free layer at a high level.

17. The electronic device of claim 14 , wherein the insertion layer includes a material blocking crystallinity that is transferred from a layer disposed below the insertion layer.

18. The electronic device of claim 17 , wherein the insertion layer includes Zr, Hf, V, Cr, Cu, Nb, Mo, Ru, Rh, Ta, W, Re or Ir, or a combination thereof.

19. The electronic device of claim 14 , wherein the second sublayer includes a Co—Fe—B alloy or a Co—Fe—B—X alloy (where, X may be Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, W or Pt).

20. The electronic device of claim 14 , wherein the first sublayer has a damping constant ranging from 0.001 to 0.1.

Assignees

• Sk Hynix Inc

Inventors

• Jung Ku-Youl
• Lim Jong-Koo
• Kim Yang-Kon
• Lee Jae-Hyoung

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L27/1222

  Electricity · mapped topic