Thru-silicon-via structures

Patent metadata

Field	Value
Publication number	US-10388567-B2
Application number	US-201715724493-A
Country	US
Kind code	B2
Filing date	Oct 4, 2017
Priority date	Jun 8, 2015
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

First claim

What is claimed:

1. A method, comprising:
forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material;
forming a stress absorption layer on the first conductive diffusion barrier liner;
forming a second conductive diffusion barrier liner on the stress absorption layer; and
forming a copper plate on the second conductive diffusion barrier liner, wherein:
the insulator layer is formed directly on sidewalls and a bottom of a trench composed of the wafer material;
the first conductive diffusion barrier liner is formed directly on the insulator layer in the trench including the sidewalls and the bottom of the trench;
the stress absorption layer is formed directly on the first conductive diffusion barrier liner within the trench including the sidewalls and the bottom of the trench;
the second conductive diffusion barrier liner is formed directly on the stress absorption layer within the trench including the sidewalls and the bottom of the trench; and
the copper plate is formed directly on the second conductive diffusion barrier liner within the trench.

2. The method of claim 1 , wherein the first conductive diffusion barrier liner is Ta or TaN.

3. The method of claim 2 , wherein the second conductive diffusion barrier liner Ta or TaN.

4. The method of claim 3 , wherein the insulator layer is an oxide material formed in contact with the wafer material.

5. The method of claim 4 , wherein the stress absorption layer is an insulator material.

6. The method of claim 5 , wherein the stress absorption layer has a Young's modulus of about 10 GPa or less.

7. The method of claim 6 , wherein the stress absorption layer has a Young's modulus of about 1.1 GPa to about 1.8 GPa.

8. The method of claim 5 , wherein the stress absorption layer is a dielectric material.

9. The method of claim 5 , wherein the stress absorption layer is a thermally degradable polymer material.

10. The method of claim 9 , wherein an upper portion of the thermally degradable polymer material is removed to form an airgap between the first conductive diffusion barrier liner and the second conductive diffusion barrier liner.

11. A method, comprising:
forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material;
forming a stress absorption layer on the first conductive diffusion barrier liner;
forming a second conductive diffusion barrier liner on the stress absorption layer;
forming a copper plate on the second conductive diffusion barrier liner; and
etching an upper portion of the stress absorption layer to form an airgap between the first conductive diffusion barrier liner and the second conductive diffusion barrier liner,
wherein the first conductive diffusion barrier liner is Ta or TaN,
wherein the second conductive diffusion barrier liner Ta or TaN,
wherein the insulator layer is an oxide material formed in contact with the wafer material,
wherein the stress absorption layer is an insulator material.

12. The method of claim 1 , wherein the stress absorption layer is deposited using a CVD process to a thickness of about 0.3 microns.

13. A method comprising:
forming a thru-silicon-via in a wafer;
lining the thru-silicon-via with an insulator material;
lining the insulator material with a diffusion barrier liner;
forming a stress absorption insulator layer on the diffusion barrier liner, the stress absorption insulator layer having a Young's modulus of about 10 GPa or less;
lining the stress absorption insulator layer with a second diffusion barrier liner;
forming a copper plate on the second diffusion barrier liner;
planarizing a surface of the wafer by removing the insulator material, diffusion barrier liner, stress absorption insulator layer, second diffusion barrier liner and copper plate from a surface of wafer which was deposited therein during the lining and forming steps;
forming a capping material on the planarized surface; and
etching an upper portion of the stress absorption insulator layer to form an airgap between the diffusion barrier liner and the second diffusion barrier liner.

14. The method of claim 13 , wherein the diffusion barrier liner and the second diffusion barrier liner are Ta or TaN.

15. The method of claim 13 , wherein the stress absorption insulator layer has a Young's modulus of about 1.1 GPa to about 1.8 GPa.

16. The method of claim 13 , wherein the stress absorption insulator layer is a dielectric material.

17. The method of claim 13 , wherein the stress absorption insulator layer is a thermally degradable polymer material.

18. The method of claim 17 , wherein an upper portion of the thermally degradable polymer material is removed to form an airgap between the diffusion barrier liner and the second diffusion barrier liner.

19. The method of claim 13 , wherein the diffusion barrier liner is directly contacting the stress absorption insulator layer.

Assignees

• Globalfoundries Inc

Inventors

• Chen Fen
• Farooq Mukta G
• Graas Carole D
• Liu Xiao Hu

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title