Spiking neural network with reduced memory access and reduced in-network bandwidth consumption

Patent metadata

Field	Value
Publication number	US-10387770-B2
Application number	US-201615062365-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Jun 10, 2015
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A spiking neural network having a plurality layers partitioned into a plurality of frustums using a first partitioning may be implemented, where each frustum includes one tile of each partitioned layer of the spiking neural network. A first tile of a first layer of the spiking neural network may be read. Using a processor, a first tile of a second layer of the spiking neural network may be generated using the first tile of the first layer while storing intermediate data within an internal memory of the processor. The first tile of the first layer and the first tile of the second layer belong to a same frustum.

First claim

What is claimed is:

1. A method comprising:
implementing a spiking neural network having a plurality of layers partitioned into a plurality of frustums using a first partitioning, wherein each frustum comprises a plurality of adjacent layers of the spiking neural network and has a three-dimensional profile having a rectangular intersection and a depth, and wherein each frustum is associated with a respective set of tiles of data of the spiking neural network, wherein an amount of data within each tile is determined by the rectangular intersection of the respective frustum, wherein implementing comprises:
reading a first tile of a first layer of a frustum; and
generating, using a processor, a first tile of a second layer of the frustum using the first tile of the first layer while storing intermediate data within an internal memory of the processor.

2. The method of claim 1 , wherein the first tile of the second layer is generated for a plurality of time intervals prior to generating another tile.

3. The method of claim 1 , wherein a size of a frustum is based, at least in part, upon a size of the internal memory and an amount of data within an input tile, an output tile, and a set of intermediate results associated with the respective frustum.

4. The method of claim 1 , wherein the intermediate data comprises post synaptic potential values and spike events.

5. The method of claim 4 , wherein the spike events are stored in an event queue in the internal memory as a plurality of masks with each mask including an x-coordinate and a y-coordinate.

6. The method of claim 1 , wherein the generating the first tile of the second layer is performed using a first compute unit of the processor, the method further comprising:
generating a second tile of the second layer using a second tile of the first layer of the spiking neural network using a second compute unit of the processor concurrently with the first compute unit.

7. The method of claim 1 , further comprising:
generating at least one tile of a further layer of the spiking neural network using a second partitioning different from the first partitioning.

8. An apparatus for implementing a spiking neural network having a plurality of layers partitioned into a plurality of frustums using a first partitioning, wherein each frustum comprises a plurality of adjacent layers of the spiking neural network and has a three-dimensional profile having a rectangular intersection and a depth, and wherein each frustum is associated with at least one respective tile of each partitioned layer, the apparatus comprising:
an internal memory configured to store intermediate data;
a first compute unit coupled to the internal memory and configured to initiate executable operations including:
reading a first tile of a first layer of a frustum; and
generating a first tile of a second layer of the frustum using the first tile of the first layer while storing intermediate data within the internal memory.

9. The apparatus of claim 8 , wherein the first tile of the second layer is generated for a plurality of time intervals prior to generating another tile.

10. The apparatus of claim 8 , wherein a size of a frustum is based, at least in part, upon a size of the internal memory and an amount of data within an input tile, an output tile, and a set of intermediate results associated with the respective frustum.

11. The apparatus of claim 8 , wherein the intermediate data comprises post synaptic potential values and spike events.

12. The apparatus of claim 11 , wherein the spike events are stored in an event queue in the internal memory as a plurality of masks with each mask including an x-coordinate and a y-coordinate.

13. The apparatus of claim 8 , further comprising:
a second compute unit configured to initiate executable operations including:
generating a second tile of the second layer using a second tile of the first layer of the spiking neural network concurrently with the first compute unit.

14. The apparatus of claim 8 , wherein the first compute unit is configured to initiate executable operations further comprising:
generating at least one tile of a further layer of the spiking neural network using a second partitioning different from the first partitioning.

15. A computer program product comprising a computer readable storage medium having program code stored thereon to implement a spiking neural network having a plurality of layers partitioned into a plurality of frustums using a first partitioning, wherein each frustum comprises a plurality of adjacent layers of the spiking neural network and has a three-dimensional profile having a rectangular intersection and a depth, and wherein each frustum is associated with a respective set of tiles of data of the spiking neural network, wherein an amount of data within each tile is determined by the rectangular intersection of the respective frustum, the program code executable by the processor to perform operations comprising:
reading a first tile of a first layer of the spiking neural network; and
generating, using a processor, a first tile of a second layer of the spiking neural network using the first tile of the first layer while storing intermediate data within an internal memory of the processor; the first tile of the first layer and the first tile of the second layer belonging to a same frustum.

16. The computer program product of claim 15 , wherein the first tile of the second layer is generated for a plurality of time intervals prior to generating another tile.

17. The computer program product 15 , wherein a size of a frustum is based, at least in part, upon a size of the internal memory and an amount of data within an input tile, an output tile, and a set of intermediate results associated with the respective frustum.

18. The computer program product 15 , wherein the intermediate data comprises post synaptic potential values and spike events.

19. The computer program product of claim 18 , wherein the spike events are stored in an event queue in the internal memory as a plurality of masks with each mask including an x-coordinate and a y-coordinate.

20. The computer program product of claim 15 , wherein the program code is executable by the processor to perform operations further comprising:
generating at least one tile of a further layer of the spiking neural network using a second partitioning different from the first partitioning.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Brothers John W
• Lee Joohoon

Classifications

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/045

  Combinations of networks · CPC title