NoC interconnect with linearly-tunable QoS guarantees for real-time isolation

Patent metadata

Field	Value
Publication number	US-10387355-B2
Application number	US-201615097091-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Apr 12, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

First claim

What is claimed is:

1. A method for operating a network-on-chip (NoC) comprising:
assigning, by the NoC, a binary port weight to a plurality of input ports of an interposer on the NoC, wherein the binary port weight is a number of traversals assigned to a respective port input of the interposer during a traversal cycle and a sum of all of the binary port weights is less than or equal to a number of traversals available to the interposer in the traversal cycle;
setting, by the NoC, a traversal counter to one at a beginning of each traversal cycle, an output of the traversal counter being a binary number of m bits, the traversal counter counting by one up to the number of traversals assigned to the interposer;
generating, by the NoC, a mask having m bits such that in response to a bit of the traversal counter transitioning from a zero to a one, the mask is generated having an m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero, where k is a bit position of a first “1”, starting from a least-significant bit position; and
transmitting, by the NoC, data from each input port to an output port in response to both the binary port weight and the mask having a one in the same bit position.

2. The method of claim 1 wherein in response to two or more of the binary port weights having a one in a same bit position after masking, the input port with a highest binary port weight is allowed a traversal in response to a mask having a one in the same bit position being generated, and the other input port is allowed a traversal during a next count of the traversal counter.

3. The method of claim 1 wherein the interposer is one of a plurality of interposers connected to a network fabric on the NoC.

4. The method of claim 3 wherein the network fabric is a folded Clos network.

5. A method for balancing data traffic on a network-on-chip (NoC), the method comprising:
assigning, by the NoC, a binary port weight to a plurality of input ports, wherein the binary port weight is a number of traversals assigned to a respective input port during a cycle and a sum of all of the binary port weights is less than or equal to a number of traversals available in the cycle;
setting, by the NoC, a traversal counter to one at a beginning of each cycle, an output of the traversal counter being a binary number of m bits, the traversal counter counting by one up to the number of traversals assigned to an interposer;
generating, by the NoC, a mask having m bits such that in response to a bit of the traversal counter transitioning from a zero to a one, the mask is generated having an m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero, where k is a bit position of the bit that has transitioned from zero to one; and
transmitting, by the NoC, data from each input port to an output port in response to both the binary port weight and the mask having a one in the same bit position.

6. The method of claim 5 wherein in response to two of the binary port weights both having a one in a same bit position in both binary port weights, the input port with a highest binary port weight is allowed a traversal in response to a mask having a one in the same bit position being generated and the other input port is allowed a traversal during a next count of the traversal counter.

7. The method of claim 5 wherein the data traffic being balanced is on a network fabric on the NoC.

8. The method of claim 7 wherein the network fabric is a folded Clos network.

9. A network-on-chip (NoC) comprising:
a network fabric of the NoC; and
a plurality of interposers of the NoC connected to the network fabric, wherein each interposer includes:
a plurality of input ports, each input port being assigned a binary port weight, wherein the binary port weight is a number of traversals assigned to a respective port during a cycle and a sum of all of the binary port weights is less than or equal to a number of traversals available in the cycle;
a traversal counter that is set to zero at a beginning of each cycle, an output of the traversal counter being a binary number of m bits, where the traversal counter counts by one up to the number of traversals assigned to the interposer; and
a mask generator generating a mask having m bits such that in response to a bit of the traversal counter transitioning from a zero to a one, the mask is generated having an m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero, where k is a bit position of the bit that has transitioned from zero to one;

wherein data is transmitted from each input port across the network fabric to an output port in response to both the binary port weight and the mask having a one in the same bit position.

10. The network of claim 9 wherein the network fabric is a folded Clos network.

11. The network of claim 9 wherein some of the plurality of interposers are arbiters that control data traffic onto the network fabric and some of the plurality of interposers control data leaving the network fabric and for each arbiter in the network fabric, the sum of all of the binary port weights, of message flows arriving at that arbiter, is less than or equal to a number of traversals available in the cycle, such that an end-to-end message latency can be bounded by Ceiling (1/BW)+1st Flit Latency through network+(# Flits/BW), where BW=binary port weight/traversals in a cycle.

12. The network of claim 9 wherein the network fabric includes queueing and arbitration mechanisms to prevent head-of-line blocking and support QoS of message flows from the interposers.

13. A network-on-chip (NoC) comprising:
a network fabric of the NoC;
a counter of the NoC having a plurality of m output ports to provide a count having m bits;
a mask generator of the NoC comprising m transition detectors, each of the transition detectors having an input connected to a respective output port of the counter,
wherein each transition detector provides a binary one on an output in response to a signal on the input transitioning from a first state to a second state,
wherein only one of the inputs transitions from the first state to the second state at each count of the counter, and
wherein a mask generated by the mask generator is reversed from the inputs of the transition detectors such that:
the output of the transition detector connected to a most significant bit of the counter is a least significant bit of the mask,
the output of the transition detector connected to a next most significant bit of the counter is a next least significant bit of the mask, and
the output of each transition detector connected to each respective next most significant bit of the counter is a next least significant bit of the mask; and

a bit-wise comparator of the NoC comparing a weighting to the mask generated by the mask generator and providing a signal to transport data across the network fabric in response to the one of the mask corresponding to a one in a corresponding bit position in the weighting.

14. A network-on-chip (NoC) comprising:
a network fabric of the NoC;
a plurality of registers of the NoC storing a plurality of binary port weights for a plurality of ports, wherein each binary port weight is a number of traversals assigned to a respective port during a cycle, and wherein a sum of all of the binary port weights is less than or equal to a number of traversals available in the cycle;
a traversal counter of the NoC that is set to zero at a beginning of each cycle, wherein an output of the traversal counter is a binary number of m bits, and wherein the traversal counter counts by one up to the number of t

Assignees

• Futurewei Technologies Inc

Inventors

• Yan Peter
• Chandra Alex Elisa
• McFearin Lee Dobson
• Yu Fang
• Gatherer Alan

Classifications

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/20

  for access to input/output bus · CPC title