Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Patent metadata

Field	Value
Publication number	US-10386904-B2
Application number	US-201615086054-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

First claim

What is claimed is:

1. A method for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
transmitting, from a DVM initiator of a processor-based system of a device to the DVM network, a DVM operation;
broadcasting, by the DVM network to each of a plurality of DVM targets physically coupled to the processor-based system of the device, the same DVM operation, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the DVM network is included in a system bus of the processor-based system of the device between the DVM initiator and the plurality of DVM targets, and wherein the DVM network combines responses to the DVM operation received from the plurality of DVM targets into a single response for the DVM initiator; and
based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network,
turning on, by a power collapse manager of the processor-based system coupled to the plurality of DVM targets and the DVM network, a power domain coupled to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the power domain being turned off, wherein the power collapse manager does not send power on requests to the plurality of DVM targets over the DVM network.

2. The method of claim 1 , wherein turning on the power domain coupled to the DVM target of the plurality of DVM targets that is the target of the DVM operation comprises:
issuing, by the power collapse manager coupled to the DVM network, a power on request to the power domain coupled to the DVM target that is the target of the DVM operation;
issuing, by the power collapse manager, a power on request to the DVM target that is the target of the DVM operation;
unblocking, by the DVM target that is the target of the DVM operation, DVM operations from the DVM network based on the power on request received from the power collapse manager;
reconnecting, by the DVM target that is the target of the DVM operation, to the DVM network; and
transmitting, by the DVM network, the DVM operation to the DVM target that is the target of the DVM operation.

3. The method of claim 2 , wherein issuing the power on request to the DVM target that is the target of the DVM operation is based on receiving, by the power collapse manager, a response from the power domain coupled to the DVM target indicating that the power domain coupled to the DVM target is turned on.

4. The method of claim 2 , further comprising:
receiving a request to power on the DVM target that is the target of the DVM operation, wherein the request is received from software being executed by the DVM initiator; and
sending a power status signal to the software indicating that the power domain coupled to the DVM target is turned on.

5. The method of claim 1 , wherein the DVM initiator comprises a processor.

6. The method of claim 1 , wherein the DVM operation comprises a translation lookaside buffer (TLB) invalidate operation, a synchronization operation, or any combination thereof.

7. The method of claim 1 , wherein the DVM initiator is coupled to a separate clock domain and a separate power domain from a clock domain and a power domain of the DVM network.

8. The method of claim 1 , wherein the plurality of DVM targets are coupled to clock domains and power domains separate from a clock domain and a power domain of the DVM initiator and a clock domain and a power domain of the DVM network.

9. The method of claim 1 , wherein each of the plurality of DVM targets is coupled to a separate clock domain and a separate power domain from remaining ones of the plurality of DVM targets.

10. The method of claim 1 , wherein the plurality of DVM targets is coupled to a single clock domain and a power domain.

11. An apparatus for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
a DVM initiator of a processor-based system of a device;
a plurality of DVM targets physically coupled to the processor-based system of the device;
a DVM network physically coupled to the DVM initiator and the plurality of DVM targets, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the DVM network is included in a system bus of the processor-based system of the device between the DVM initiator and the plurality of DVM targets, wherein the DVM network is configured to broadcast the same DVM operation from the DVM initiator to each of the plurality of DVM targets, and wherein the DVM network combines responses to the DVM operation received from the plurality of DVM targets into a single response for the DVM initiator,
wherein, based on a DVM operation in the DVM network being broadcasted to the plurality of DVM targets,
a power collapse manager of the processor-based system coupled to the plurality of DVM targets and the DVM network is configured to turn on a power domain coupled to the DVM target of the plurality of DVM targets that is the target of the DVM operation based on the power domain being turned off, wherein the power collapse manager does not send power on requests to the plurality of DVM targets over the DVM network.

12. The apparatus of claim 11 , wherein the one or more memory management units each comprise a translation lookaside buffer (TLB).

13. The apparatus of claim 11 , wherein the DVM initiator comprises a processor.

14. The apparatus of claim 11 , wherein the DVM operations comprise a TLB invalidate operations, synchronization operations, or any combination thereof.

15. The apparatus of claim 11 , wherein the DVM initiator is coupled to a separate clock domain and a separate power domain from a clock domain and a power domain of the DVM network.

16. The apparatus of claim 11 , wherein the plurality of DVM targets are coupled to clock domains and power domains separate from a clock domain and a power domain of the DVM initiator and a clock domain and a power domain of the DVM network.

17. The apparatus of claim 11 , wherein each of the plurality of DVM targets is coupled to a separate clock domain and a separate power domain from remaining ones of the plurality of DVM targets.

18. The apparatus of claim 11 , wherein the plurality of DVM targets is coupled to a single clock domain and a power domain.

19. The apparatus of claim 11 , wherein the DVM network reports the single response to the DVM initiator.

20. An apparatus for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network, comprising:
means for broadcasting of a processor-based system of a device communicatively coupled to a plurality of DVM targets coupled to the processor-based system of the device; and
means for transmitting of the processor-based system of the device, to the means for broadcasting, a DVM operation, wherein the plurality of DVM targets comprises a plurality of memory management units, wherein the means for broadcasting is included in a system bus of the processor-based system of the device between the means for transmitting and the plurality of DVM targets, wherein the means for broadcasting is configured to broadcast, to each of the plurality of DVM targets, the same DVM operation, and wherein the means for broadcasting is configured to combine responses to the DVM operation received from the plurality of DVM targets into a single response for the means for transmitting,
wherein, based on the DVM operation being broadcasted to th

Assignees

• Qualcomm Inc

Inventors

• Podaima Jason Edward
• Avoinne Christophe Denis Bernard
• SOMASUNDARAM Manokanthan
• DENA Sina
• Wiercienski Paul Christopher John
• Rychlik Bohuslav
• Halter Steven John
• Subramaniam Ganasan Jaya Prakash
• RAMKUMAR Myil
• Pal Dipti Ranjan

Classifications

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title