Control gate dummy for word line uniformity and method for producing the same

Patent metadata

Field	Value
Publication number	US-10381360-B1
Application number	US-201815933069-A
Country	US
Kind code	B1
Filing date	Mar 22, 2018
Priority date	Mar 22, 2018
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

First claim

What is claimed is:

1. A method comprising:
providing a substrate having a memory cell (MCEL) region, a high voltage (HV) region and a logic region, separated by an isolation region;
forming a plurality of control gate (CG) stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively;
forming first and second overlying polysilicon layers with a spacer therebetween, an erase gate (EG) and a word line (WL) on the MCEL region formed, wherein forming the EG on the MCEL region comprises:
forming a source region in the MCEL region of the Si substrate by an N-type dopant implant; and
oxidizing an upper portion of the source region;

planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and
removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

2. The method according to claim 1 , comprising forming the plurality of CG stacks and the plurality of CG dummy stacks by:
forming an oxide layer over the Si substrate;
forming a floating gate (FG) over the oxide layer;
forming an interpoly dielectric (IPD) over the FG;
forming a control gate (CG) and a CG hardmask (HM), respectively, over the IPD; and
forming a plurality of trenches through the CG HM, the CG, the IPD, the FG and the oxide layer.

3. The method according to claim 1 , comprising planarizing the second polysilicon layer by chemical mechanical polishing (CMP).

4. The method according to claim 1 , comprising removing portions of the second polysilicon by a polysilicon etch back (EB) process or reactive ion etching (RIE).

5. The method according to claim 1 , wherein the isolation region comprises a shallow trench isolation (STI), and wherein the STI further comprising:
forming an oxide liner over the STI; and
forming an insulating material over the oxide liner.

6. The method according to claim 2 , further comprising:
forming nitride and oxide spacers, respectively, on sidewalls of the plurality of CG stacks and the plurality of CG dummy stacks prior to forming the first and second polysilicon layers.

7. The method according to claim 2 , further comprising forming the EG on the MCEL region by:
forming nitride and oxide spacers on sidewalls of the CG stack; and
forming polysilicon.

8. The method according to claim 2 , comprising forming the FG and CG of polysilicon.

9. The method according to claim 2 , comprising forming the IPD of an oxide/nitride/oxide stack, and the CG HM of a nitride/oxide/nitride stack.

10. A device comprising:
a substrate having a memory cell (MCEL) region, a high voltage (HV) region and a logic region, separated by an isolation region;
a plurality of control gate (CG) stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region with isolation region in-between;
a first spacer and a second spacer on sidewalls of the plurality of CG stacks and the plurality of CG dummy stacks;
an erase gate (EG) and a word line (WL) on the MCEL region, wherein the EG further comprises:
a source region in the MCEL region of the Si substrate; and
a silicon oxide over the source region; and

a polysilicon layer within the EG, the WL and adjacent to the plurality of CG dummy stacks, wherein the polysilicon within the EG is coplanar with the polysilicon within the WL.

11. The device according to claim 10 , wherein the polysilicon layer adjacent to the plurality of CG dummy stacks over the HV region and the logic region comprises a third spacer.

12. The device according to claim 10 , wherein the plurality of CG stacks and the plurality of CG dummy stacks comprises:
an oxide layer over a portion of the Si substrate;
a floating gate (FG) over the oxide layer;
an interpoly dielectric (IPD) over the FG; and
a control gate (CG) and a CG hardmask (HM), respectively, over the IPD.

13. The device according to claim 10 , wherein:
the first spacer comprises nitride; and
the second spacer comprises oxide.

14. The device according to claim 10 , wherein the isolation region comprises a shallow trench isolation (STI), and wherein the STI further comprises:
an oxide liner over the STI; and
an insulating material over the oxide liner.

15. The device according to claim 11 , wherein:
the FG and CG comprise polysilicon;
the IPD comprises an oxide/nitride/oxide stack; and
the CG HM comprises a nitride/oxide/nitride stack.

16. A method comprising:
providing a silicon (Si) substrate having a memory cell (MCEL) region, a high voltage (HV) region and a logic region, respectively, separated by a shallow trench isolation (STI);
forming a plurality of control gate (CG) stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively;
forming a first polysilicon layer over the Si substrate;
forming a spacer over portions of the first polysilicon layer over the HV region and the logic region;
forming a second polysilicon layer over the first polysilicon layer and the spacer, an erase gate (EG) and a word line (WL) on the MCEL region formed, wherein forming the EG on the MCEL region comprises:
forming a source region in the MCEL region of the Si substrate by an N-type dopant implant; and
oxidizing an upper portion of the source region;

planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks by chemical mechanical polishing (CMP); and
removing portions of the second polysilicon layer in-between the plurality of CG stacks and adjacent to the plurality of CG dummy stacks by a polysilicon etch back (EB) process or reactive ion etching (RIE).

17. The method according to claim 16 , comprising forming the plurality of CG stacks and the plurality of CG dummy stacks by:
forming an oxide layer over the Si substrate;
forming a floating gate (FG) over the oxide layer;
forming an interpoly dielectric (IPD) over the FG;
forming a control gate (CG) and a CG hardmask (HM), respectively, over the IPD; and
forming a plurality of trenches through the CG HM, the CG, the IPD, the FG and the oxide layer.

18. The method according to claim 16 , further comprising:
forming nitride and oxide spacers on sidewalls of the plurality of CG stacks and the plurality of CG dummy gate stacks prior to forming the first and second polysilicon layers.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Luo Laiqiang
• Mei Sen
• Deng Fangxin
• Teo Zhiqiang
• Zhang Fan
• Li Pinghui
• Zhou Haiqing
• Chen Xingyu
• Pey Kin Leong

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title