Common boosted assist

Patent metadata

Field	Value
Publication number	US-10381054-B1
Application number	US-201815906588-A
Country	US
Kind code	B1
Filing date	Feb 27, 2018
Priority date	Feb 27, 2018
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.

First claim

What is claimed:

1. A structure comprising an assist circuit which comprises a read logic circuit and a write logic circuit such that the assist circuit is configured to add a boost voltage using a common boost logic device for both the read logic circuit and the write logic circuit of the assist circuit,
wherein the write logic circuit comprises a write logic core, a write logic, the common boost logic device, and at least one bitline,
the read logic circuit comprises a read logic core, a read logic, a sense amplifier, and the at least one bitline, and
the sense amplifier is directly connected to the added boost voltage through a boost signal such that the sense amplifier is configured to receive the added boost voltage during a read operation.

2. The structure of claim 1 , wherein the assist circuit is configured to add the boost voltage to the read logic circuit during the read operation using the common boost logic device.

3. The structure of claim 2 , wherein the assist circuit is configured to stop the boost voltage from being added to the write logic circuit during the read operation, using the common boost logic device.

4. The structure of claim 1 , wherein the assist circuit is configured to add the boost voltage to the write logic circuit during a write operation, using the common boost logic device.

5. The structure of claim 4 , wherein the assist circuit is configured to stop the boost voltage from being added to the read logic circuit during the write operation, using the common boost logic device.

6. The structure of claim 4 , wherein the at least one bitline receives the added boost voltage during the write operation.

7. The structure of claim 1 , wherein the common boost logic device is at least one NMOS transistor which is configured to control whether the boost voltage is added to the read logic circuit or the write logic circuit.

8. The structure of claim 1 , wherein the write logic circuit comprises at least one NOR gate which is configured to avoid charge leak from boost data during the read operation or a write operation.

9. The structure of claim 1 , wherein the assist circuit is included in at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), and a single ended sense amplifier design.

10. A circuit, comprising:
a read logic circuit which comprises a read logic core, a read logic, a sense amplifier, and at least one bitline and is configured to sense a differential voltage through the sense amplifier during a read operation;
a write logic circuit which comprises a write logic core, a write logic, a common boost logic device, and the at least one bitline and is configured to write a data value through the at least one bitline during a write operation; and
the common boost logic device is configured to add a boost voltage to one of the read logic circuit and the write logic circuit,
wherein the sense amplifier is directly connected to the added boost voltage through a boost signal such that the sense amplifier is configured to receive the added boost voltage during the read operation.

11. The circuit of claim 10 , wherein the at least one bitline of the write logic circuit does not receive the added boost voltage during the read operation.

12. The circuit of claim 10 , wherein the at least one bitline of the write logic circuit receives the added boost voltage during the write operation.

13. The circuit of claim 12 , wherein the sense amplifier of the read logic circuit does not receive the added boost voltage during the write operation.

14. The circuit of claim 10 , wherein the common boost logic device is at least one NMOS transistor which is configured to control whether the boost voltage is added to the read logic circuit or the write logic circuit.

15. The circuit of claim 10 , wherein the write logic circuit comprises at least one NOR gate which is configured to avoid charge leak from boost data during the read operation or the write operation.

16. The circuit of claim 10 , further comprising an assist circuit which includes the read logic circuit and the write logic circuit, and the assist circuit is included in at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), and a single ended sense amplifier design.

17. A method, comprising:
adding a boost voltage to a read logic circuit of an assist circuit using a common boost logic device during a read operation;
adding the boost voltage to a write logic circuit of the assist circuit using the common boost logic device during a write operation; and
preventing data from being propagated through the write logic circuit during the read operation,
wherein the write logic circuit comprises a write logic core, a write logic, the common boost logic device, and at least one bitline,
the read logic circuit comprises a read logic core, a read logic, a sense amplifier, and the at least one bitline, and
the sense amplifier is directly connected to the added boost voltage through a boost signal such that the sense amplifier is configured to receive the added boost voltage during a read operation.

18. The method of claim 17 , wherein the common boost logic device is at least one NMOS transistor and a charge leak is avoided from boost data during the read operation or the write operation using at least one NOR gate.

19. The structure of claim 1 , further comprising a NOR gate in the assist circuit which receives a write selection signal and a sense amplifier enable signal and outputs a complement boost signal to a boosted capacitor of the assist circuit.

20. The structure of claim 19 , wherein the boosted capacitor is connected between the complement boost signal and the boost signal, the boost signal is directly connected to the write logic circuit through a first NMOS transistor and is directly connected to the read logic circuit through a second NMOS transistor, the first NMOS transistor is gated by the complement boost signal and has a source connected to ground, and the second NMOS transistor is gated by the sense amplifier enable signal and has a source connected to the boost signal.

Assignees

• Globalfoundries Inc

Inventors

• Sreenivasula Reddy Dhani Reddy
• Bhat Soori Vinay

Classifications

• G11C11/407

  for memory cells of the field-effect type · CPC title

• G11C5/145 Primary

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C11/409

  Read-write [R-W] circuits · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title