Pixel unit driving circuit, driving method and display apparatus for pixel unit using alternately switching elements having inverted polarities

US10380959B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10380959-B2
Application numberUS-201615325025-A
CountryUS
Kind codeB2
Filing dateJan 25, 2016
Priority dateAug 26, 2015
Publication dateAug 13, 2019
Grant dateAug 13, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a pixel unit driving circuit, a driving method and a display apparatus. According to the present disclosure, pixel units in a panel are designed to use switch elements of the pixel units made of NMOS transistors and PMOS transistors alternately. That is, the switch elements connected to scan signal lines and data lines use NMOS transistors and PMOS transistors alternately in the horizontal (vertical) direction. In conjunction with a scan timing sequence, a high-low level time division scan technique can be adopted to allow the voltage difference between the data lines and the pixel electrodes to vary alternately between positive and negative.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel unit driving circuit for driving a light emitting element of a pixel unit, comprising: a plurality of scan signal lines each configured to provide a scan signal; a plurality of data lines each configured to provide a data signal, and a plurality of pixel units, each comprising a switch element connected to one of the scan signal lines and one of the data lines; wherein the switch elements of the plurality of pixel units comprising n-type or p-type elements, wherein the scan signal lines and the data lines are cross-connected with respective switch elements of the pixel unit to constitute a pixel unit driving circuit in a matrix form, and wherein switch elements in each row of pixel units use alternately inverted switch types, the switch elements in each row of pixel units that have the N-type elements are directly connected to a first scan signal line, the switch elements in each row of pixel units that have the P-type elements are directly connected to a second scan signal line that is adjacent to the first scan signal line, and wherein switch elements that directly connect to the same scan signal line have the same types; and wherein the scan signal lines connected to the respective switch elements are configured to drive the respective switch elements with alternate high and low levels. 2. The pixel unit driving circuit of claim 1 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements alternately. 3. The pixel unit driving circuit of claim 2 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements of the pixel units in a same row alternately in odd and even columns. 4. The pixel unit driving circuit of claim 2 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements of the pixel units in a same row alternately in odd and even rows. 5. The pixel unit driving circuit of claim 1 , wherein the polarities of the switch elements alternate at an interval of a plurality of rows or columns. 6. The pixel unit driving circuit of claim 1 , wherein the polarities of the respective switch elements alternate at an interval of one pixel. 7. The pixel unit driving circuit of claim 1 , wherein the scan signal lines in odd rows are connected to the switch elements having one polarity and the scan signal lines in even rows are connected to the switch elements having the other polarity. 8. A display apparatus, comprising the pixel unit driving circuit according to claim 1 . 9. The display apparatus of claim 8 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements alternately. 10. The display apparatus of claim 9 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements of the pixel units in a same row alternately in odd and even columns. 11. The display apparatus of claim 9 , wherein NMOS transistors and PMOS transistors are used as the respective switch elements of the pixel units in a same row alternately in odd and even rows. 12. The display apparatus of claim 8 , wherein the polarities of the switch elements alternate at an interval of a plurality of rows or columns. 13. The display apparatus of claim 8 , wherein the polarities of the respective switch elements alternate at an interval of one pixel. 14. The display apparatus of claim 8 , wherein the scan signal lines in odd rows are connected to the switch elements having one polarity and the scan signal lines in even rows are connected to the switch elements having the other polarity. 15. The display apparatus of claim 8 , wherein the switch elements in two adjacent rows of pixel units that have the same switch type are connected to a same scan signal line. 16. The display apparatus of claim 8 , wherein the types of switch elements in each row of pixel units alternate at an interval of one or more columns. 17. The pixel unit driving circuit of claim 1 , wherein the switch elements in two adjacent rows of pixel units that have the same switch type are connected to a same scan signal line. 18. The pixel unit driving circuit of claim 1 , wherein the pixel units in odd columns in ith row are driven by the ith scan signal line, and the pixel units in even column in ith row are driven by the (i+1)th scan signal line, wherein i is a positive integer. 19. The pixel unit driving circuit of claim 1 , wherein the types of switch elements in each row of pixel units alternate at an interval of one or more columns.

Assignees

Inventors

Classifications

  • Several active elements per pixel in active matrix panels · CPC title

  • Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

  • G09G3/3614Primary

    Control of polarity reversal in general · CPC title

  • Layout of electrodes and connections · CPC title

  • suitable for active matrices only · CPC title

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Frequently asked questions

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What does patent US10380959B2 cover?
The present disclosure provides a pixel unit driving circuit, a driving method and a display apparatus. According to the present disclosure, pixel units in a panel are designed to use switch elements of the pixel units made of NMOS transistors and PMOS transistors alternately. That is, the switch elements connected to scan signal lines and data lines use NMOS transistors and PMOS transistors al…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Chengdu Boe Optoelect Tech Co
What technology area does this patent fall under?
Primary CPC classification G09G3/3614. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 13 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).