Half-bridge fingeprint sensing method

Patent metadata

Field	Value
Publication number	US-10380397-B2
Application number	US-201514978442-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Sep 9, 2015
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Fingerprint detection circuits with common mode noise rejection are described. The Fingerprint detection circuit includes a half-bridge circuit coupled to a receive (RX) electrode of an array of fingerprint detection electrodes and to a buried capacitance that is unalterable by the presence of a conductive object on the array. The fingerprint detection circuit may also include a listener electrode configured to enable common mode noise rejection through a differential input stage of a low noise amplifier (LNA).

First claim

What is claimed is:

1. A differential capacitance measurement circuit comprising:
a half-bridge circuit comprising a first mutual capacitor and a second mutual capacitor coupled to a first input of an amplifier;
a listener electrode coupled to a second input of the amplifier; and
a compensation circuit comprising:
a modulator;
a buffer coupled to an output of the modulator, the buffer configured to output a compensation signal; and
a compensation capacitor coupled between an output of the buffer and the first input of the amplifier.

2. The differential capacitance measurement circuit of claim 1 , wherein the buffer configured to output the compensation signal oscillates between a programmable voltage and a ground potential.

3. The differential capacitance measurement circuit of claim 1 , further comprising:
a first buffer configured to provide a first transmit signal to a first node of the first mutual capacitor; and
a second buffer configured to provide a second transmit signal to a first node of the second mutual capacitor.

4. The differential capacitance measurement circuit of claim 3 , wherein the first transmit signal and the second transmit signal are 180 degrees out of phase.

5. The differential capacitance measurement circuit of claim 3 , further comprising:
a third buffer configured to provide a third transmit signal to a first node of a third mutual capacitance, wherein the third mutual capacitance is coupled to the first input of the amplifier; and
control logic for providing control signals to the second and third buffers.

6. The differential capacitance measurement circuit of claim 5 , wherein the first and third transmit signal are in-phase.

7. The differential capacitance measurement circuit of claim 1 , wherein the listener electrode is configured to couple to a conductive object and provide common mode noise rejection at the second input of the amplifier.

8. A method for measuring a capacitance comprising:
receiving a first signal derived from the capacitance on a receive node, the receive node coupled to a first input of an amplifier;
receiving a second signal derived from a buried capacitance on the receive node;
receiving a third signal on a listener electrode, the listener electrode coupled to a second input of the amplifier;
generating a differential output of the amplifier;
converting the differential output of the amplifier to a digital value representative of the capacitance; and
receiving a fourth signal on the receive node, wherein the fourth signal is configured to provide a compensation current to the input of the amplifier, and wherein the fourth signal is produced by a modulator coupled to a buffer, which is coupled to a compensation capacitor coupled to the first input of the amplifier.

9. The method of claim 8 , wherein the first signal on the receive node is generated by a first transmit signal on a first node of a capacitor and received on a second node of the capacitor coupled to the receive node.

10. The method of claim 8 , wherein the second signal on the receive node is generated by a second transmit signal on a first node of a capacitor and received on a second node of the capacitor coupled to the receive node.

11. The method of claim 10 , wherein the capacitor is formed by a drive electrode and a buried receive electrode.

12. The method of claim 8 , wherein the second signal is defined by control logic coupled to a buffer, the buffer comprising an output coupled to transmit electrode and the receive node coupled to a receive electrode.

Assignees

• Cypress Semiconductor Corp

Inventors

• Kravets Igor
• Ogirko Roman
• Klein Hans
• Hoshtanar Oleksandr

Classifications

• G06K9/0002 Primary

  Physics · mapped topic

• G06V40/1306 Primary

  non-optical, e.g. ultrasonic or capacitive sensing · CPC title