Validation of circuit definitions

Patent metadata

Field	Value
Publication number	US-10380298-B2
Application number	US-201414160859-A
Country	US
Kind code	B2
Filing date	Jan 22, 2014
Priority date	Aug 18, 2011
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.

First claim

What is claimed is:

1. A method for use in validating a circuit design, the method implemented in a computing device comprising:
accessing by the computing device circuit information specifying a plurality of connections between a plurality of components of at least a portion of the circuit design;
retrieving at the computing device from a plurality of parametric models a respective parametric model for each of the plurality of components specified in the accessed circuit information, each of the parametric models specifying a pin type, from a plurality of pin types, and operating parameters of each pin of the associated component;
determining at the computing device a plurality of checks to apply to at least the portion of the circuit design based on the pin types of the plurality of components, wherein each of the plurality checks, when applied to at least the portion of the circuit design, determines one or more characteristics of at least the portion of the circuit design;
applying at the computing device the plurality of determined checks to at least the portion of the circuit design to identify potential errors resulting from interconnections between components of the portion of the circuit design;
generating at the computing device test results for at least the portion of the circuit design from the applied plurality of determined checks; and
displaying the generated test results.

2. The method of claim 1 , wherein the plurality of pin types are a predefined set of pin types.

3. The method of claim 1 , wherein the circuit information comprises a netlist comprising a plurality of nets specifying the plurality of connections between a plurality of component references and a Bill Of Material (BOM) associating each of the plurality of component references with a respective component.

4. The method of claim 3 , wherein determining the plurality of checks to apply comprises determining checks to apply to each net of the netlist.

5. The method of claim 3 , wherein determining the plurality of checks to apply comprises:
determining extended nets for each net in the netlist; and
determining checks to apply to each of the determined extended nets.

6. The method of claim 5 , wherein determining checks to apply to each of the determined extended nets comprises:
determining a composition of pin types in the respective extended net; and
selecting a subset of checks from a plurality of checks based on the pin type composition of the extended net.

7. The method of claim 1 , wherein one or more of the plurality parametric models comprises a plurality of operating parameters for a pin of the associated component, each associated with a selecting condition for selecting its use with the component, the method further comprising:
determining one of the operating parameters of the pin to use based on the selecting condition.

8. The method of claim 7 , wherein the selecting condition specifies an operating parameter of another pin of the associated component, and determining one of the operating parameters comprises determining the operating parameter of the other pin based on one or more connected components.

9. The method of claim 7 , wherein the selecting condition is associated with a parameter of the associated component.

10. The method of claim 7 , wherein the selecting condition specifies a characteristic value of the associated component.

11. The method of claim 7 , wherein the selecting condition is based on an operating characteristic of the associated component.

12. The method of claim 1 , wherein accessing the circuit information comprises receiving the circuit information from a circuit design tool.

13. The method of claim 12 , wherein the portion of the circuit design comprises a net in the circuit that was modified by the circuit design tool.

14. The method of claim 13 , wherein displaying the generated test results comprises displaying the generated test results in the circuit design tool.

15. The method of claim 1 , wherein each of the parametric models specify one or more of:
a pin number;
a pin name;
the pin type;
a maximum input voltage;
a minimum input voltage;
an input voltage representing a logic level high;
an input voltage representing a logic level low;
a maximum output voltage;
a minimum output voltage;
an output voltage representing a logic level high;
an output voltage representing a logic level low;
a driver qualifier specifying a voltage for selecting one of a plurality of operating parameters for a pin;
a driver power rail specifying a pin associated with the driver qualifier;
a maximum supply voltage; and
a minimum supply voltage.

16. A system for validating a circuit design comprising:
a processor for executing instructions; and
a memory for storing instructions, the instructions when executed by the processor configuring the system to:
access circuit information specifying a plurality of connections between a plurality of components of at least a portion of the circuit design;
retrieve from a plurality of parametric models a respective parametric model for each of the plurality of components specified in the accessed circuit information, each of the parametric models specifying a pin type, from a plurality of pin types, and operating parameters of each pin of the associated component;
determine a plurality of checks to apply to at least the portion of the circuit design based on the pin types of the plurality of components, wherein each of the plurality checks, when applied to at least the portion of the circuit design, determines one or more characteristics of at least the portion of the circuit design;
apply the plurality of determined checks to at least the portion of the circuit design to identify potential errors resulting from interconnections between components of the portion of the circuit design;
generate test results for at least the portion of the circuit design from the applied plurality of determined checks; and
display the generated test results.

17. The system of claim 16 , wherein the plurality of pin types are a predefined set of pin types.

18. The system of claim 16 , wherein the circuit information comprises a netlist comprising a plurality of nets specifying the plurality of connections between a plurality of component references and a Bill Of Material (BOM) associating each of the plurality of component references with a respective component.

19. The system of claim 18 , wherein configuring the system to determine the plurality of checks to apply comprises configuring the system to determine checks to apply to each net of the netlist.

20. The system of claim 18 , wherein configuring the system to determine the plurality of checks to apply comprises configuring the system to:
determine extended nets for each net in the netlist; and
determine checks to apply to each of the determined extended nets.

21. The system of claim 20 , wherein configuring the system to determine checks to apply to each of the determined extended nets comprises configuring the system to:
determine a composition of pin types in the respective extended net; and
select a subset of checks from a plurality of checks based on the pin type composition of the extended net.

22. The system of claim 16 , wherein one or more of the plurality parametric models comprises a plurality of operating parameters for a pin of the associated component, each associated with a selecting condition for selecting its use with the comp

Assignees

• Mentor Graphics Corp

Inventors

• Alam Michael
• Campbell Peter
• Cianfaglione Mark

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5022

  Physics · mapped topic

• G06F17/5045 Primary

  Physics · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/30

  Circuit design · CPC title