Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state

Patent metadata

Field	Value
Publication number	US-10379870-B2
Application number	US-201715644670-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Jul 7, 2017
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

First claim

We claim:

1. A method of initializing a secondary processor pursuant to a soft reboot of system software, said method comprising:
storing code to be executed by the secondary processor in a region of physical memory;
building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space;
fetching a first instruction of the code from a first location in the physical memory based on a first virtual address and active page tables, wherein the first virtual address is a virtual address in the first address space;
executing the code beginning with the first instruction to switch the active page tables from the first page tables to the second page tables; and
after the active page tables have been switched from the first page tables to the second page tables, (i) fetching a next instruction of the code to be executed from a second location in the physical memory using a second virtual address, which is identically mapped to a corresponding machine address, (ii) turning off a memory management unit of the secondary processor, and (iii) executing a waiting loop until a predetermined location in the physical memory changes in value, and (iv) exiting the waiting loop and executing an initialization code at a physical memory address corresponding to the changed value.

2. The method of claim 1 , further comprising:
storing the second virtual address in a register prior to executing the code; and
reading the second virtual address from the register in response to a page fault resulting from the switch of the active page tables from the first page tables to the second page tables.

3. The method of claim 2 , further comprising:
after the active page tables have been switched from the first page tables to the second page tables and prior to fetching the next instruction, flushing a translation lookaside buffer of the memory management unit of the secondary processor.

4. The method of claim 2 , wherein the first virtual address and the second virtual address map to the same machine address.

5. The method of claim 1 , further comprising:
adding entries to the second page tables to map the code into the second address space at the same virtual addresses as the first address space.

6. The method of claim 5 , further comprising:
after the active page tables have been switched from the first page tables to the second page tables and prior to fetching the next instruction, determining a next virtual address in the second address space corresponding to a next instruction of the code to be executed and computing the second virtual address by adding an offset to the next virtual address,
wherein the offset is a difference between two starting virtual addresses in the second address space to which the code is mapped.

7. The method of claim 6 , wherein the first virtual address and the second virtual address map to different machine addresses.

8. The method of claim 1 , further comprising:
while executing the waiting loop, waiting for an event issued by a primary processor.

9. A non-transitory computer readable medium comprising instructions to be executed in a secondary processor pursuant to a soft reboot of system software, wherein the instructions, when executed in the secondary processor, cause the secondary processor to perform a method comprising:
storing code to be executed by the secondary processor in a region of physical memory;
building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space;
fetching a first instruction of the code from a first location in the physical memory based on a first virtual address and active page tables, wherein the first virtual address is a virtual address in the first address space;
executing the code beginning with the first instruction to switch the active page tables from the first page tables to the second page tables; and
after the active page tables have been switched from the first page tables to the second page tables, (i) fetching a next instruction of the code to be executed from a second location in the physical memory using a second virtual address, which is identically mapped to a corresponding machine address, (ii) turning off a memory management unit of the secondary processor, and (iii) executing a waiting loop until a predetermined location in the physical memory changes in value, and (iv) exiting the waiting loop and executing an initialization code at a physical memory address corresponding to the changed value.

10. The non-transitory computer readable medium of claim 9 , wherein the method further comprises:
storing the second virtual address in a register prior to executing the code; and
reading the second virtual address from the register in response to a page fault resulting from the switch of the active page tables from the first page tables to the second page tables.

11. The non-transitory computer readable medium of claim 10 , wherein the method further comprises:
after the active page tables have been switched from the first page tables to the second page tables and prior to fetching the next instruction, flushing a translation lookaside buffer of the memory management unit of the secondary processor.

12. The non-transitory computer readable medium of claim 11 , wherein the first virtual address and the second virtual address map to the same machine address.

13. The non-transitory computer readable medium of claim 9 , wherein the method further comprises:
adding entries to the second page tables to map the code into the second address space at the same virtual addresses as the first address space.

14. The non-transitory computer readable medium of claim 13 , wherein the method further comprises:
after the active page tables have been switched from the first page tables to the second page tables and prior to fetching the next instruction, determining a next virtual address in the second address space corresponding to a next instruction of the code to be executed and computing the second virtual address by adding an offset to the next virtual address, wherein the offset is a difference between two starting virtual addresses in the second address space to which the code is mapped.

15. The non-transitory computer readable medium of claim 14 , wherein the first virtual address and the second virtual address map to different machine addresses.

16. The non-transitory computer readable medium of claim 9 , wherein the method further comprises:
while executing the waiting loop, waiting for an event issued by a primary processor.

17. A computer system comprising:
a primary processor running system software; and
one or more secondary processors,
wherein, when the primary processor initiates a soft reboot of the system software, each of the secondary processors performs the steps of:
storing code to be executed by the secondary processor in a region of physical memory;
building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space;
fetching a first instruction of the code from a first location in the physical memory based on a first virtual address and active page tables, wherein the first virtual address is a virtual address in the first address space;
executing the code beginning with the first instruction to switch the active page tables from the first page tables to the second page tables; and
after the active page tables have been switched from the first page

Assignees

• Vmware Inc

Inventors

• Warkentin Andrei
• Laplace Cyprien
• Duchesne Regis
• Fainkichen Alexander
• Li Ye

Classifications

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title