Display apparatus

Patent metadata

Field	Value
Publication number	US-10379415-B2
Application number	US-201715626441-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Jun 24, 2016
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

According to an aspect, a display apparatus includes: a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and a driver configured to drive the display panel. The pixel transistor includes: at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor.

First claim

What is claimed is:

1. A display apparatus comprising:
a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and
a driver configured to drive the display panel, wherein
the pixel transistor includes:
at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and
a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor,

wherein the scanning line includes:
a first scanning line coupled to a gate of the at least one NMOS transistor; and
a second scanning line coupled to a gate of the at least one PMOS transistor,

wherein the driver comprises a gate driver configured to:
generate and supply, to the first scanning line, an NMOS gate drive signal to drive the gate of the at least one NMOS transistor; and
generate and supply, to the second scanning line, a PMOS gate drive signal to drive the gate of the at least one PMOS transistor,
wherein the NMOS gate drive signal has polarity inverted from polarity of the PMOS gate drive signal,
wherein a lower potential of the NMOS gate drive signal is lower than a voltage lower limit value of a signal supplied to the video signal line, and
wherein a higher potential of the PMOS gate drive signal is higher than a voltage upper limit value of the signal supplied to the video signal line,
wherein a higher potential of the NMOS gate drive signal is equal to a middle value of a potential difference between the voltage upper limit value and the voltage lower limit value of the signal supplied to the video signal line, and
wherein a lower potential of the PMOS gate drive signal is equal to the middle value of the potential difference between the voltage upper limit value and the voltage lower limit value of the signal supplied to the video signal line.

2. The display apparatus according to claim 1 , wherein
the at least one NMOS transistor comprises a plurality of NMOS transistors,
the at least one PMOS transistor comprises a plurality of PMOS transistors, and
in the pixel transistor, the NMOS transistors are coupled in series between the video signal line and the pixel capacitor, and the PMOS transistors, the number of which is identical to that of the NMOS transistors, are coupled in series between the video signal line and the pixel capacitor.

3. A display apparatus comprising:
a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and
a driver configured to drive the display panel,
wherein the pixel transistor includes:
at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and
a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor,

wherein the scanning line includes:
a first scanning line coupled to a gate of the at least one NMOS transistor; and
a second scanning line coupled to a gate of the at least one PMOS transistor,

wherein the driver comprises a gate driver configured to:
generate and supply, to the first scanning line, an NMOS gate drive signal to drive the gate of the at least one NMOS transistor; and
generate and supply, to the second scanning line, a PMOS gate drive signal to drive the gate of the at least one PMOS transistor,

wherein the NMOS gate drive signal has polarity inverted from polarity of the PMOS gate drive signal,
wherein a lower potential of the NMOS gate drive signal is lower than a voltage lower limit value of a signal supplied to the video signal line, and
a higher potential of the PMOS gate drive signal is higher than a voltage upper limit value of the signal supplied to the video signal line, and
wherein a higher potential of the NMOS gate drive signal is higher than a middle value of a potential difference between the voltage upper limit value and the voltage lower limit value of the signal supplied to the video signal line.

4. The display apparatus according to claim 3 , wherein
the at least one NMOS transistor comprises a plurality of NMOS transistors,
the at least one PMOS transistor comprises a plurality of PMOS transistors, and in the pixel transistor, the NMOS transistors are coupled in series between the video signal line and the pixel capacitor, and the PMOS transistors, the number of which is identical to that of the NMOS transistors, are coupled in series between the video signal line and the pixel capacitor.

5. A display apparatus comprising:
a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and
a driver configured to drive the display panel,
wherein the pixel transistor includes:
at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and
a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor,

wherein the scanning line includes:
a first scanning line coupled to a gate of the at least one NMOS transistor; and
a second scanning line coupled to a gate of the at least one PMOS transistor,

wherein the driver comprises a gate driver configured to:
generate and supply, to the first scanning line, an NMOS gate drive signal to drive the gate of the at least one NMOS transistor; and
generate and supply, to the second scanning line, a PMOS gate drive signal to drive the gate of the at least one PMOS transistor,

wherein the NMOS gate drive signal has polarity inverted from polarity of the PMOS gate drive signal,
wherein a lower potential of the NMOS gate drive signal is lower than a voltage lower limit value of a signal supplied to the video signal line, and
a higher potential of the PMOS gate drive signal is higher than a voltage upper limit value of the signal supplied to the video signal line, and
wherein a lower potential of the PMOS gate drive signal is lower than a middle value of a potential difference between the voltage upper limit value and the voltage lower limit value of the signal supplied to the video signal line.

6. The display apparatus according to claim 5 , wherein
the at least one NMOS transistor comprises a plurality of NMOS transistors,
the at least one PMOS transistor comprises a plurality of PMOS transistors, and
in the pixel transistor, the NMOS transistors are coupled in series between the video signal line and the pixel capacitor, and the PMOS transistors, the number of which is identical to that of the NMOS transistors, are coupled in series between the video signal line and the pixel capacitor.

Assignees

• Japan Display Inc

Inventors

• Katsuta Tadayoshi

Classifications

• G09G3/344

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title