System and method for providing power savings in an access point via ethernet rate and interface shifting

Patent metadata

Field	Value
Publication number	US-10375633-B2
Application number	US-201615374572-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Dec 9, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Disclosed is a method for managing bus channels between a physical layer and a media access channel layer of a network. The method includes determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture. When the current rate changes to yield a new link speed, the method includes determining a minimal (or near minimal) bus size required to implement the new link speed and switching to the minimal bus size between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture. The method further includes switching to the minimal bus size between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture.

First claim

What is claimed is:

1. A method for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the method comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

2. The method of claim 1 , wherein the minimal bus size comprises a SerDes lane.

3. The method of claim 1 , wherein the minimal bus size comprises a plurality of SerDes lanes.

4. The method of claim 1 , wherein the plurality of buses comprise one or more of SGMII, 2500BASE-X, and RXAUI.

5. The method of claim 1 , wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

6. The method of claim 1 , wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.

7. A system for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the system comprising:
a processor; and
a computer-readable storage device storing instructions which, when executed by the processor, cause the processor to perform operations comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

8. The system of claim 7 , wherein the minimal bus size comprises one of a SerDes lane or a plurality of SerDes lanes.

9. The system of claim 7 , wherein the plurality of buses comprise SGMII, 2500BASE-X, and RXAUI.

10. The system of claim 7 , wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

11. The system of claim 7 , wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.

12. A non-transitory computer-readable storage device storing instructions for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the instructions when executed by a processor cause the processor to perform operations comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

13. The non-transitory computer-readable storage device of claim 12 , wherein the minimal bus size comprises one of a SerDes lane or a plurality of SerDes lanes.

14. The non-transitory computer-readable storage device of claim 12 , wherein the plurality of buses comprise one or more of SGMII, 2500BASE-X, and RXAUI.

15. The non-transitory computer-readable storage device of claim 12 , wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

16. The non-transitory computer-readable storage device of claim 12 , wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.

Assignees

• Cisco Tech Inc

Inventors

• Carty Clark
• Duckworth Daniel
• Pleso Mark

Classifications

• H04W52/0206

  in access points, e.g. base stations · CPC title

• H04W88/08

  Access point devices · CPC title

• Y02D70/00

  Cross-Sectional Technologies · mapped topic

• H04W52/0212 Primary

  managed by the network, e.g. network or access point is leader and terminal is follower · CPC title

• Y02D30/70

  in wireless communication networks · CPC title