Increasing communication safety by preventing false packet acceptance in high-speed links

Patent metadata

Field	Value
Publication number	US-10374751-B2
Application number	US-201615154153-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Jun 25, 2013
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years.

First claim

What is claimed is:

1. A method for preventing false packet acceptance, comprising:
operating the high-speed link under a mode in which correctable symbol errors are corrected while uncorrectable symbol errors are passed through without marking;
detecting a correctable symbol error ratio (SER) for a high-speed link which employs forward error correction (FEC);
disconnecting or temporarily pausing the high-speed link if the correctable SER exceeds a predetermined threshold to prevent false packet acceptance,
wherein disconnecting the high-speed link comprises continuously corrupting block sync headers to generate a hi_ber condition for a predetermined period and disconnecting the link after the predetermined period.

2. The method of claim 1 , wherein the predetermined threshold is set such that the correctable SER is one of approximately 6.6e-5 or approximately 1.3e-3.

3. The method of claim 1 , further comprising determining the predetermined threshold using a statistical model such that a mean time to false packet acceptance (MTTFPA) exceeds a predetermined value.

4. The method of claim 3 , wherein the MTTFPA is approximately at least 15 billion years.

5. The method of claim 4 , wherein the high-speed link is configured to operate such that it has a projected mean time to disconnect (MTTD) of at least 100 years.

6. An apparatus comprising:
Physical Layer (PHY) circuitry, including,
a transmitter port including transmitter circuitry for four transmit lanes; and
a receiver port including receiver circuitry for four receive lanes;
a Physical Coding Sublayer (PCS) module including a bit error ratio (BER) monitor;
a Reed-Solomon Forward Error Correction (RS-FEC) module coupled to the PCS module and configured to,
detect correctable symbol errors;
correct the correctable symbol errors;
pass through uncorrectable symbol errors without marking; and
determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold,

wherein the apparatus is further configured to be implemented in a high-speed link and disconnect or temporarily pause the high-speed link when it is determined the correctable SER exceeds the correctable SER threshold to prevent false packet acceptance, and
wherein in response to detection of a correctable SER exceeding the correctable SER threshold the RS-FEC module is configured to forward blocks with corrupted sync headers to the PCS module, and the BER monitor is configured to detect the corrupted sync headers and generate a hi_ber condition.

7. The apparatus of claim 6 , wherein the correctable SER threshold is one of approximately 6.6e-5 or approximately 1.3e-3.

8. The apparatus of claim 6 , wherein the PHY circuitry is configured to be implemented in an Ethernet link employing Media Access Channel (MAC) frames using a 32-bit Cyclic Redundancy Check (CRC32), and wherein the correctable SER threshold is determined using a statistical model such that a mean time to false packet acceptance (MTTFPA) for MAC frames exceeds approximately 15 billion years.

9. The apparatus of claim 8 , wherein the Ethernet link is configured to operate such that it has a projected mean time to disconnect (MTTD) of at least 100 years.

10. The apparatus of claim 6 , wherein the PCS module includes a bit error ratio (BER) monitor, and wherein in response to detection of a correctable SER exceeding the correctable SER threshold the RS-FEC module is configured to forward blocks with corrupted sync headers to the PCS module, and the BER monitor is configured to detect the corrupted sync headers and generate a hi_ber condition.

11. An apparatus comprising:
Physical Layer (PHY) circuitry, including,
a transmitter port including transmitter circuitry for four transmit lanes; and
a receiver port including receiver circuitry for four receive lanes;
a Physical Coding Sublayer (PCS) module;
a Reed-Solomon Forward Error Correction (RS-FEC) module coupled to the PCS module;

a Media Access Control (MAC) module;
a Reconciliation Sublayer (RS) module; and
a Peripheral Component Interconnect Express (PCIe) interface;
wherein the RS-FEC module is configured to,
pass through uncorrectable symbol errors without marking;
detect correctable symbol errors;
correct the correctable symbol errors; and
determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold,

wherein the apparatus is further configured to be implemented in a high-speed link and in response to determining a correctable SER exceeds the correctable SER threshold continuously corrupt block sync headers to generate a hi_ber condition for a predetermined period and disconnect or temporarily pause the high-speed link after the predetermined period to prevent false packet acceptance.

12. The apparatus of claim 11 , wherein the correctable SER threshold is one of approximately 6.6e-5 or approximately 1.3e-3.

13. The apparatus of claim 11 , wherein the PHY circuitry is configured to be implemented in an Ethernet link employing Media Access Control (MAC) frames using a 32-bit Cyclic Redundancy Check (CRC32), and wherein the correctable SER threshold is determined using a statistical model such that a mean time to false packet acceptance (MTTFPA) for MAC frames exceeds approximately 15 billion years.

14. The apparatus of claim 13 , wherein the wherein the Ethernet link is configured to operate such that it has a projected mean time to disconnect (MTTD) of at least 100 years.

15. A system comprising:
a chassis;
an inter-plane, mounted within the chassis, having first and second inter-plane connectors and wiring coupled therebetween configured to facilitate a multi-lane 100 Gigabits per second (Gb/s) Ethernet link;
a first board having a first network interface controller (NIC) including 100 Gb/s Ethernet transmitter and receiver ports operatively coupled to a first board connector that is coupled to the first inter-plane connector;
a second board having a second NIC including 100 Gb/s Ethernet transmitter and receiver ports operatively coupled to a second board connector that is coupled to the second inter-plane connector,
wherein the 100 Gb/s Ethernet transmitter for each of the first and second NICs is configured to transmit data over four transmit lanes, and the first NIC is configured, when the system is operating,
receive data from the second NIC via the 100 Gb/s Ethernet link;
pass through uncorrectable symbol errors without marking;
detect correctable symbol errors and correct the correctable symbol errors;
determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold; and,
in response thereto,
continuously corrupt block sync headers to generate a hi_ber condition for a predetermined period and disconnect the 100 Gb/s Ethernet link after the predetermined period to prevent false packet acceptance.

16. The system of claim 15 , wherein the correctable SER threshold is one of approximately 6.6e-5 or approximately 1.3e-3.

17. The system of claim 15 , wherein the PHY circuitry is configured to be implemented in an Ethernet link employing Media Access Channel (MAC) frames using a 32-bit Cyclic Redundancy Check (CRC32), and wherein the correctable SER threshold is determined using a statistical model such that a mean time to false packet acceptance (MTTFPA) for MAC frames exceeds approximately 15 billion years.

18. The system of claim 15 , wherein the PCS module includes a bit error ratio (BER) monitor, and wherein in response to detection of a correctable SER exceeding the SER threshold the RS-FEC module is con

Assignees

• Intel Corp

Inventors

• Ran Adee O

Classifications

• H04L1/0045 Primary

  Arrangements at the receiver end · CPC title

• H04L1/0038

  Blind format detection (for detection of modulation format H04L27/0012) · CPC title

• H04L1/203

  Details of error rate determination, e.g. BER, FER or WER · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L1/245

  by using the properties of transmission codes · CPC title