Systems and methods of relocking for locked loops

Patent metadata

Field	Value
Publication number	US-10374651-B1
Application number	US-201816147658-A
Country	US
Kind code	B1
Filing date	Sep 29, 2018
Priority date	Sep 29, 2018
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.

First claim

What is claimed is:

1. An apparatus comprising:
a locked loop including:
a loop configured to run responsive to a run signal, the loop including:
a memory state component; and
signal characteristic adjustment circuitry coupled to the memory state component, the signal characteristic adjustment circuitry configured to produce an output signal having a characteristic that is based on the memory state component; and

a locked-loop controller coupled to the loop, the locked-loop controller configured to:
receive an external power mode signal;
generate the run signal to have an enable value at a first time when the external power mode signal is indicative of an external normal mode; and
generate the run signal to have the enable value at a second time when the external power mode signal is indicative of an external standby mode.

2. The apparatus of claim 1 , wherein the locked-loop controller is configured, while the external power mode signal is indicative of the external standby mode, to:
cause the loop to run to substantially lock to a reference signal at the second time during an external standby mode period; and
cause the loop to cease running at a third time during the external standby mode period.

3. The apparatus of claim 1 , further comprising:
an external power manager configured to:
provide the external power mode signal to the locked loop and to a device component separate from the locked loop; and
drive the external power mode signal to indicate the external standby mode and the external normal mode.

4. The apparatus of claim 3 , wherein the locked-loop controller is configured to generate the run signal to have an enable value responsive to the external power mode signal being changed from the external standby mode to the external normal mode.

5. The apparatus of claim 3 , wherein the locked-loop controller is configured to generate the run signal to have a disable value at a third time when the external power mode signal is indicative of the external standby mode.

6. The apparatus of claim 5 , wherein:
the locked-loop controller includes an internal power manager;
the internal power manager includes a timer; and
the internal power manager is configured to, responsive to the external power mode signal being indicative of the external standby mode, cycle at least between providing the run signal with the enable value and providing the run signal with the disable value based on the timer.

7. The apparatus of claim 1 , wherein the locked-loop controller is configured to override the external power mode signal by enabling the loop to run and update the memory state component during the external standby mode.

8. The apparatus of claim 7 , wherein:
the memory state component comprises an accumulator that is configured to have a memory state, and the accumulator is configured to store a digital value as the memory state; or
the memory state component comprises a capacitor that is configured to have a memory state, and the capacitor is configured to store a voltage differential as the memory state.

9. The apparatus of claim 1 , wherein the locked loop is configured to gate one or more signals from external circuitry at least during the external standby mode.

10. The apparatus of claim 1 , wherein:
the locked loop comprises a frequency locked loop (FLL);
the output signal has a frequency; and
the signal characteristic adjustment circuitry comprises a variable oscillator configured to adjust the frequency of the output signal based on the memory state component.

11. The apparatus of claim 1 , wherein:
the locked loop comprises a phase locked loop (PLL);
the output signal has a phase; and
the signal characteristic adjustment circuitry comprises a variable oscillator configured to adjust the phase of the output signal based on the memory state component.

12. The apparatus of claim 1 , wherein:
the locked loop comprises a delay locked loop (DLL);
the output signal is associated with a delay; and
the signal characteristic adjustment circuitry comprises a variable delay circuit configured to adjust the delay associated with the output signal based on the memory state component.

13. The apparatus of claim 1 , wherein the locked-loop controller includes an internal power manager configured to generate an internal power mode signal, the internal power mode signal indicative of a series of power modes over time including multiple internal pause modes and multiple internal run modes.

14. The apparatus of claim 13 , wherein the locked-loop controller is configured to enable the loop to run responsive to the external power mode signal being indicative of an external normal mode regardless of a power mode indicated by the internal power mode signal.

15. The apparatus of claim 13 , wherein the locked-loop controller is configured to enable the loop to run responsive to the external power mode signal being indicative of the external standby mode and to the internal power mode signal being indicative of an internal run mode of the multiple internal run modes.

16. The apparatus of claim 13 , wherein the locked-loop controller is configured to disable the loop from running responsive to the external power mode signal being indicative of the external standby mode and to the internal power mode signal being indicative of an internal pause mode of the multiple internal pause modes.

17. The apparatus of claim 13 , wherein each internal run mode of the multiple internal run modes has a duration that is sufficient to enable the loop to substantially lock the output signal to a reference signal after a memory state of the memory state component drifts during an internal pause mode of the multiple internal pause modes.

18. The apparatus of claim 1 , wherein the locked-loop controller is configured to cause repetitive current spike events by the locked loop while the external power mode signal is indicative of the external standby mode.

19. The apparatus of claim 18 , wherein the loop is configured to exhibit the current spike events as the loop repetitively draws a current with an increased magnitude while running in a feedback mode to repeatedly return the loop to a substantially locked state during the external standby mode.

20. The apparatus of claim 1 , wherein the locked-loop controller is configured to keep the loop warm during the external standby mode to reduce a relocking duration that elapses after the external standby mode is terminated relative to a relocking duration for a cold loop.

21. The apparatus of claim 1 , further comprising a sensor, wherein:
the locked-loop controller includes an internal power manager; and
the internal power manager is configured to, responsive to the external power mode signal being indicative of the external standby mode, cycle at least between providing the run signal with the enable value and providing the run signal with a disable value based on information from the sensor.

22. A system comprising:
a locked loop including:
a loop configured to provide an output signal responsive to a run signal; and
control means for periodically keeping the loop warm responsive to an external power mode signal being indicative of an external standby mode, the control means configured to provide the run signal to the loop.

23. The system of claim 22 , wherein:
the system comprises a wireless transceiver; and
the locked loop comprises a frequency locked loop (FLL).

24. The system

Assignees

• Qualcomm Inc

Inventors

• Sivakumar Shyam Sundar
• Wang Kevin Jia-Nong

Classifications

• H03L7/10 Primary

  for assuring initial synchronisation or for broadening the capture range · CPC title

• H03L7/103

  the additional signal being a digital signal · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H04B1/403 Primary

  using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency · CPC title

• H04B1/006

  using switches for selecting the desired band (H04B1/0057 takes precedence) · CPC title