Method and system for LDPC decoding

Patent metadata

Field	Value
Publication number	US-10374633-B2
Application number	US-201715619764-A
Country	US
Kind code	B2
Filing date	Jun 12, 2017
Priority date	Jul 8, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

First claim

What is claimed is:

1. A method for Low-Density Parity-Check (LDPC) decoding, the method comprising: receiving a soft-decision input codeword block, wherein the probability of a bit being a “0” or a “1” is represented in the soft-decision input codeword block as a log-likelihood ratio (LLR); and iteratively updating the soft-decision input codeword block, by a sequence of hardware logic units, until a valid codeword is found or a maximum number of decoding iterations is reached, wherein each decoding iteration comprises a check node (CN) phase followed by a variable node (VN) phase, and wherein each hardware logic unit of the sequence of hardware logic units is operably coupled to receive input from a first other hardware logic unit of the sequence of hardware logic units and provide output to a second other hardware logic unit of the sequence of hardware logic units, wherein each hardware logic unit of the sequence of hardware logic units operates in series during the CN phase, thereby: generating a CN-to-VN message, generating an intermediate LLR and a VN-to-CN message according to the CN-to-VN message, and storing the VN-to-CN message in a memory for use during the CN phase in a next iteration, wherein each hardware logic unit of the sequence of hardware logic units operates in series during the VN phase, thereby performing a piecewise parity check, such that a final parity value across a plurality of connected VNs is determined by the last hardware logic unit of the sequence of hardware logic units.

2. The method for LDPC decoding of claim 1 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having at least one all-zero sub-matrix.

3. The method for LDPC decoding of claim 2 , wherein the method comprises bypassing a hardware logic unit according to the placement of the all-zero sub-matrix in the parity-check matrix.

4. The method for LDPC decoding of claim 1 , wherein the method comprises iteratively update the soft-decision input codeword block during the VN phase of each decoding iteration of a plurality of decoding iterations.

5. The method for LDPC decoding of claim 1 , wherein the method comprises propagating a plurality of intermediate CN update values during the CN phase of each decoding iteration of a plurality of decoding iterations.

6. The method for LDPC decoding of claim 5 , wherein the plurality of intermediate CN update values comprises a parity value, a sign value, and at least one minimum magnitude value.

7. The method for LDPC decoding of claim 5 , wherein the method comprises updating the CN-to-VN message according to the plurality of intermediate CN update values.

8. The method for LDPC decoding of claim 5 , wherein the method comprises generating the VN-to-CN message according to the plurality of intermediate CN update values.

9. The method for LDPC decoding of claim 1 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having a plurality of independent routing layers, wherein the plurality of independent routing layers are processed in parallel by each hardware logic unit of the sequence of hardware logic units.

10. The method for LDPC decoding of claim 1 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having a plurality of columns, wherein the plurality of columns are processed in parallel by each hardware logic unit of the sequence of hardware logic units.

11. A Low-Density Parity-Check (LDPC) decoder, the LDPC decoder comprising: an interface operable to receive a soft-decision input codeword block, wherein the probability of a bit being a “0” or a “1” is represented in the soft-decision input codeword block as a log-likelihood ratio (LLR); a sequence of hardware logic units, each hardware logic unit comprising a check node (CN) update logic unit and a variable node (VN) update logic unit, wherein each hardware logic unit of the sequence of hardware logic units is operably coupled to receive input from a first other hardware logic unit of the sequence of hardware logic units and provide output to a second other hardware logic unit of the sequence of hardware logic units; a closed CN path between the CN update logic unit in each hardware logic unit of the sequence of hardware logic units, wherein the closed CN path is operable to propagate a plurality of intermediate CN update values during a first pass of each decoding iteration of a plurality of decoding iterations; and a closed VN path between the VN update logic unit in each hardware logic unit of the sequence of hardware logic units, wherein each VN update logic unit is operable to iteratively update the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached.

12. The LDPC decoder of claim 11 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having at least one all-zero sub-matrix.

13. The LDPC decoder of claim 12 , wherein a hardware logic unit corresponding to the all-zero sub-matrix in the parity-check matrix comprises a CN update logic unit with bypass circuitry and a VN update logic unit with bypass circuitry.

14. The LDPC decoder of claim 11 , wherein a CN update logic unit is operable to generate a CN-to-VN message and update an intermediate LLR according to the CN-to-VN message.

15. The LDPC decoder of claim 11 , wherein the VN update logic unit in the last hardware logic unit of the sequence of hardware logic units is operable to determine whether the valid codeword is found based on a piecewise parity check performed via the closed VN path.

16. The LDPC decoder of claim 15 , wherein the CN update logic unit is operable to update a CN-to-VN message according to the plurality of intermediate CN update values.

17. The LDPC decoder of claim 15 , wherein the CN update logic unit is operable to generate a VN-to-CN message according to the plurality of intermediate CN update values.

18. The LDPC decoder of claim 11 , wherein the plurality of intermediate CN update values comprises a parity value, a sign value, and at least one minimum magnitude value.

19. The LDPC decoder of claim 11 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having a plurality of independent routing layers, wherein each hardware logic unit of the sequence of hardware logic units is operable to process the plurality of independent routing layers in parallel.

20. The LDPC decoder of claim 11 , wherein the soft-decision input codeword block corresponds to an LDPC encoded signal generated from a parity-check matrix having a plurality of columns, wherein each hardware logic unit of the sequence of hardware logic units is operable to process the plurality of columns in parallel.

Assignees

• Maxlinear Inc

Inventors

• Milicevic Mario
• Gulak Glenn

Classifications

• H03M13/114

  Shuffled, staggered, layered or turbo decoding schedules · CPC title

• H03M13/3746

  with iterative decoding · CPC title

• H03M13/635

  Error control coding in combination with rate matching · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/1122

  storing only the first and second minimum values per check node · CPC title