High-voltage switching circuit, corresponding device and method

Patent metadata

Field	Value
Publication number	US-10374600-B2
Application number	US-201816122262-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Sep 7, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals.

First claim

The invention claimed is:

1. A circuit, including:
a first comparator and a second comparator having respective differential inputs configured for receiving input signals of opposed polarities, the first comparator and the second comparator having respective output nodes,
a first reference current generator,
a switch driven by the output nodes of the first and second comparators, the switch having an input coupled to the first reference current generator and configured to transfer a first current output from the first reference current generator alternatively to a first node and a second node in response to the output nodes of the first and second comparators,
a pair of second reference current generators, coupled to the first node and the second node, respectively, wherein second currents of the pair of second reference current generators are applied to the first node and the second node, respectively, with a sign opposite to a sign of the first current, and
a logic circuit having a first input coupled to the first node and a second input coupled to the second node so as to receive first and second switching signals each having fast switching wavefronts and delayed switching wavefronts, wherein the logic circuit includes an output node and is configured to switch the output node between a first state and a second state, wherein switching between the first state and the second state is triggered by the fast switching wavefronts of said first and second switching signals.

2. The circuit of claim 1 , wherein the second currents each have an intensity that is half of an intensity of the first current.

3. The circuit of claim 1 , wherein the logic circuit comprises:
a first pulse generator coupled to the first input;
a second pulse generator coupled to the second input; and
a latch circuit having set and reset inputs driven by the first pulse generator and the second pulse generator, respectively.

4. The circuit of claim 1 , wherein:
the first comparator and the second comparator are coupled to a first circuit ground, and
the pair of second reference current generators and the logic circuit are coupled to a second circuit ground, wherein the second circuit ground is floating with respect to the first circuit ground.

5. The circuit of claim 1 , wherein the first input and the second input of the logic circuit are coupled to the first node and the second node via logical inverter circuits.

6. The circuit of claim 1 , wherein the pair of second reference current generators are coupled with respective voltage-limiting zener diodes.

7. The circuit of claim 3 , wherein the first pulse generator and the second pulse generator include low-pass circuits controlling durations of set and reset pulses applied to the set and reset inputs of the latch circuit.

8. The circuit of claim 7 , wherein the first pulse generator and the second pulse generator include NAND logic gates with a first input configured for receiving said respective switching signals and a second input configured for receiving delayed replicas of said respective switching signals.

9. The circuit of claim 8 , wherein the first pulse generator and the second pulse generator include a low-pass network coupled to the second inputs of the NAND logic gates to low-pass filter said delayed replicas.

10. The circuit of claim 1 , further including a user circuit coupled to the output node wherein switching of the output node between the first state and the second state is substantially unaffected by the delayed switching wavefronts of said respective switching signals.

11. The circuit of claim 1 , wherein the input signals of opposed polarities include a DC signal having superposed thereon a square wave signal.

12. A circuit, comprising:
a first current source configured to generate a first current;
a switch having an input configured to receive the first current, a first output and a second output;
a first comparator configured to compare a first input signal to a second input signal and in response thereto cause the switch to connect the input to the first output;
a second comparator configured to compare the second input signal to the first input signal and in response thereto cause the switch to connect the input to the second output;
a second current source configured to sink a second current from the first output;
a third current source configured to sink a third current from the second output; and
a latch circuit having a set input coupled to receive a first signal from the first output and a reset input coupled to receive a second signal from the second output.

13. The circuit of claim 12 , further comprising:
a first inverter configured to invert the first signal from the first output before application to the set input; and
a second inverter configured to invert the second signal from the second output before application to the reset input.

14. The circuit of claim 13 , wherein the first and second inverters are referenced to a first ground node, and wherein the first and second comparators are referenced to a second ground node, and wherein the second ground node is floating relative to the first ground node.

15. The circuit of claim 12 , further comprising:
a first diode coupled in parallel to the second current source; and
a second diode coupled in parallel to the third current source.

16. The circuit of claim 12 , wherein the latch circuit is a NAND latch.

17. The circuit of claim 12 , further comprising:
a first pulse generator configured to generate a first pulse from the first signal for application to the set input; and
a second pulse generator configured to generate a second pulse from the second signal for application to the reset input.

18. The circuit of claim 17 , wherein the first pulse generator and the second pulse generator each include a low-pass circuit configured to control a duration of the first and second pulses, respectively.

Assignees

• St Microelectronics Srl

Inventors

• Mirabella Ignazio Bruno
• Alessandro Agatino Antonino

Classifications

• H03K17/284 Primary

  in field effect transistor switches · CPC title

• H03K17/08104

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K2017/0803

  against radiation hardening · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title