Semiconductor device

Patent metadata

Field	Value
Publication number	US-10374102-B2
Application number	US-201815889098-A
Country	US
Kind code	B2
Filing date	Feb 5, 2018
Priority date	Mar 25, 2013
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A semiconductor device includes first to fourth semiconductor regions, and first and second electrodes. The second semiconductor region is selectively disposed in a surface layer of one main surface of the first semiconductor region. The first electrode is in contact with a contact region of the second semiconductor region. The third semiconductor region is disposed in a surface layer on another main surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region. The second electrode is in contact with the third semiconductor region. The fourth semiconductor region of the second conductivity type is disposed in the first semiconductor region, and disposed closer to the one main surface than the third semiconductor region. The fourth semiconductor region is disposed at least within the contact region in a plan view.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a plurality of fourth semiconductor regions of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor regions being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor regions being disposed inside and outside the contact region in a plan view of the semiconductor device, the fourth semiconductor regions extending in a direction parallel to the another main surface and being spaced from each other;
a second electrode in contact with the third semiconductor region; and
a fifth semiconductor region of the first conductivity type, the fifth semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region and lower than the impurity concentration of the third semiconductor region, the fifth semiconductor region being disposed in the first semiconductor region, and being closer to the one main surface than is each of the fourth semiconductor regions, the fifth semiconductor region having a Schottky junction contacting the second electrode.

2. The semiconductor device according to claim 1 , wherein an occupation area ratio of a surface area of the plurality of fourth semiconductor regions to a surface area of an active region in which a main current flows is equal to or greater than 90% and no greater than 98%.

3. The semiconductor device according to claim 1 , wherein one of the fourth semiconductor regions has a length in a direction parallel to the another main surface equal to or greater than 250 μm.

4. The semiconductor device according to claim 1 , wherein the semiconductor device satisfies
L 1≥{( q·μ·d·Np·Vbi )/ J} 1/2

where L 1 is a length of one of the fourth semiconductor regions in a direction parallel to the one surface, J is a current density of a main current that flows through an active region, q is an elementary charge, μ is hole mobility, d is a thickness of the one of the fourth semiconductor regions in a depth direction, Np is an impurity concentration of the fourth semiconductor regions, and Vbi is a built-in potential of a pn junction between the one of the fourth semiconductor regions and the third semiconductor region.

5. The semiconductor device according to claim 1 , wherein the distance between the outermost periphery of the contact region and the outermost periphery of one of the fourth semiconductor regions in the plan view is equal to or less than 2000 μm.

6. The semiconductor device according to claim 1 , wherein
the first semiconductor region has a rectangular shape with a first side in a first direction and a second side in second direction perpendicular to the first direction, in the plan view,
one of the fourth semiconductor regions has a shape with a third side that is parallel to the first side and a fourth side that is parallel to the second side.

7. The semiconductor device according to claim 1 , wherein the outermost periphery of one of the fourth semiconductor regions is located inside of the third semiconductor region in the plan view.

8. A semiconductor device, comprising
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a plurality of fourth semiconductor regions of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor regions being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor regions being disposed inside and outside the contact region in a plan view of the semiconductor device, the fourth semiconductor regions extending in a direction parallel to the another main surface and being spaced from each other by gaps, the plurality of fourth semiconductor regions including
a plurality of first fourth semiconductor regions, each of which is disposed inside of the contact region, and
a plurality of second fourth semiconductor regions, each of which is disposed outside of the contact region; and

a second electrode in contact with the third semiconductor region, wherein
the semiconductor device includes first to fourth areas in the plan view,
the first area being outside of the contact region, and having an area size A 20 ,
the second area being a total area of surfaces of the second fourth semiconductor regions, and having an area size A 21 in total,
the third area being inside of the contact region, and having an area size A 10 ,
the fourth area being a total area of surfaces of the first fourth semiconductor regions and having an area size A 11 in total, and

the area sizes A 20 , A 21 , A 10 and A 11 satisfy A 21 /A 20 <A 11 /A 10 .

9. The semiconductor device according to claim 8 , wherein each gap between two adjacent ones of the plurality of second fourth semiconductor regions is greater than each gap between two adjacent ones of the plurality of first fourth semiconductor regions.

10. A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device; and
a second electrode in contact with the third semiconductor region, wherein
a distance between an outermost periphery of the contact region and an outermost periphery of the fourth semiconductor region within the contact region in the plan vi

Assignees

• Fuji Electric Co Ltd

Inventors

• Onozawa Yuichi
• Yoshimura Takashi
• Takishita Hiroshi

Classifications

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P34/40

  with high-energy radiation · CPC title

• H10P32/1406

  by ion implantation · CPC title