Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-10373971-B2
Application number	US-201715487761-A
Country	US
Kind code	B2
Filing date	Apr 14, 2017
Priority date	Aug 19, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, the method comprising:
forming stacks each including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween;
forming a conductive pattern filling the interlayer space and deviating from the interlayer space; and
forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process, wherein a boundary between the isolation layer and a non-oxidized portion of the conductive pattern is disposed within the slit,
the forming of the conductive pattern comprises:
forming a first conductive pattern through the slit, the first conductive pattern filling a portion of the interlayer space and surrounding the channel laver; and
forming a second conductive pattern on the first conductive pattern, the second conductive pattern including a first portion filling a remaining portion of the interlayer space and a second portion extending outwardly to an outside of the interlayer space from the first portion,

wherein the forming of the first conductive pattern comprises:
forming a first conductive layer through the slit to fill the interlayer space; and
etching the first conductive layer so that the first conductive layer is removed from the slit and remains on a portion of the interlayer space,

wherein a conductive material remains on edges of the interlayer insulating layers adjacent to the slit during the forming of the first conductive pattern or the second conductive pattern, and
wherein the conductive material is oxidized in the oxidizing process.

2. The method of claim 1 , wherein the forming of the stacks comprises:
alternately stacking the interlayer insulating layers and sacrificial layers;
forming the channel layer penetrating the interlayer insulating layers and the sacrificial layers;
forming the slit penetrating the interlayer insulating layers and the sacrificial layers; and
opening the interlayer space between the interlayer insulating layers adjacent to one another by removing the sacrificial layers through the slit.

3. The method of claim 1 , wherein the forming of the second conductive pattern comprises growing the second conductive pattern from the first conductive pattern by using a selective growth method that uses the first conductive pattern as a seed layer.

4. The method of claim 3 , wherein the growing of the second conductive pattern is performed so that the second conductive pattern extends to an inside of the slit.

5. The method of claim 1 , wherein the first conductive pattern and the second conductive pattern are formed of substantially a same metal.

6. The method of claim 1 , wherein the second conductive pattern has a resistivity greater than the first conductive pattern.

7. The method of claim 1 , wherein the forming of the isolation layer is performed so that a portion of the conductive pattern protrudes further than edges of the interlayer insulating layers adjacent to the list and remains in a non-oxidized state.

8. The method of claim 1 , wherein the conductive pattern includes tungsten.

9. The method of claim 1 , wherein the oxidizing process includes a thermal oxidation or a radical oxidation.

10. The method of claim 1 , wherein the conductive patterns have a greater volume than the interlayer spaces.

11. The method of claim 1 , wherein the isolation layer is formed on a sidewall of the conductive pattern facing the slit.

12. The method of claim 1 , wherein the oxidizing portion of the conductive pattern is a portion of the conductive pattern protruding toward the slit.

Assignees

• Sk Hynix Inc

Inventors

• Park Hae Chan
• Kim Jang Won
• SA Gong Hyun

Classifications

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title