Semiconductor device

Patent metadata

Field	Value
Publication number	US-10373952-B2
Application number	US-201615042603-A
Country	US
Kind code	B2
Filing date	Feb 12, 2016
Priority date	Mar 26, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.

First claim

What is claimed is:

1. A semiconductor device comprising a first transistor and a second transistor connected to a first power supply,
the first transistor including:
a first gate insulating film provided over a semiconductor substrate;
a first gate electrode provided over the first gate insulating film;
a first source region and a first drain region which are provided in the semiconductor substrate respectively on both sides of the first gate electrode and contain impurities of a first conductivity type;
first impurity regions which are provided on inner sides of the first source region and the first drain region in the semiconductor substrate, respectively, and which contain impurities of the first conductivity type, lower ends of the first impurity regions being located at shallower positions than lower ends of the first source region and the first drain region;
a first channel region provided in the semiconductor substrate between the first impurity regions; and
a second impurity region which is provided in the semiconductor substrate under the first channel region and contains impurities of a second conductivity type different from the first conductivity type in a higher concentration than the first channel region, and which comes in directly contact with the first impurity regions, the first source region and the first drain region, and
the second transistor including:
a second gate insulating film provided over the semiconductor substrate;
a second gate electrode provided over the second gate insulating film;
a second source region and a second drain region which are provided in the semiconductor substrate respectively on both sides of the second gate electrode and contain impurities of the first conductivity type;
third impurity regions which are provided on inner sides of the second source region and the second drain region in the semiconductor substrate, respectively, and which contain impurities of the first conductivity type, lower ends of the third impurity regions being located at shallower positions than lower ends of the second source region and the second drain region;
a second channel region provided in the semiconductor substrate between the third impurity regions; and
a fourth impurity region which is provided in the semiconductor substrate under the second channel region and contains impurities of the second conductivity type in a higher concentration than the second channel region, and which comes in directly contact with the third impurity regions, the second source region and the second drain region, wherein
a thickness of the first gate insulating film is larger than a thickness of the second gate insulating film; and
a concentration of the impurities of the second conductivity type contained in the second impurity region is lower than a concentration of the impurities of the second conductivity type contained in the fourth impurity region, and wherein
the first transistor has a first characteristic in which a first sub-threshold leak current decreases and a first junction leak current increases as a bias being applied to the semiconductor substrate increases;
the second transistor has a second characteristic in which a second sub-threshold leak current decreases and a second junction leak current increases as a bias being applied to the semiconductor substrate increases;
in the first transistor, a first sum of the first sub-threshold leak current and the first junction leak current when a first bias is applied to the semiconductor substrate has a first minimum value;
in the second transistor, a second sum of the second sub-threshold leak current and the second junction leak current when a second bias is applied to the semiconductor substrate has a second minimum value; and
the first minimum value of the first sum is smaller than the second minimum value of the second sum.

2. The semiconductor device according to claim 1 , wherein
the first power supply has a voltage not higher than 1 V.

3. The semiconductor device according to claim 1 , wherein
a common bias is applied to the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein
a single bias generation circuit is electrically connected to the semiconductor substrate of the first transistor and the second transistor.

5. The semiconductor device according to claim 1 further comprising a third transistor connected to a second power supply having a higher voltage than the first power supply,
the third transistor including:
a third gate insulating film which is provided over the semiconductor substrate and has a larger thickness than the first gate insulating film;
a third gate electrode provided over the third gate insulating film; and
a third source region and a third drain region provided in the semiconductor substrate respectively on both sides of the third gate electrode.

6. The semiconductor device according to claim 1 further comprising a third transistor connected to a second power supply having a higher voltage than the first power supply,
the third transistor including:
a third gate insulating film which is provided over the semiconductor substrate and has a thickness substantially equal to a thickness of the first gate insulating film;
a third gate electrode provided over the third gate insulating film; and
a third source region and a third drain region provided in the semiconductor substrate respectively on both sides of the third gate electrode.

7. The semiconductor device according to claim 1 further comprising a fourth transistor connected to the first power supply,
the fourth transistor including:
a fourth gate insulating film which is provided over the semiconductor substrate and has a thickness substantially equal to a thickness of the first gate insulating film;
a fourth gate electrode which is provided over the fourth gate insulating film and has a larger gate length than the first gate electrode;
a fourth source region and a fourth drain region which are provided in the semiconductor substrate respectively on both sides of the fourth gate electrode and contain impurities of the first conductivity type;
a fourth channel region provided in the semiconductor substrate between the fourth source region and the fourth drain region, and
a fifth impurity region which is provided in the semiconductor substrate under the fourth channel region and contains impurities of the second conductivity type in a higher concentration of the second conductivity type than the fourth channel region.

8. The semiconductor device according to claim 1 , further comprising a fifth transistor connected to the first power supply,
the fifth transistor including:
a fifth gate insulating film which is provided over the semiconductor substrate and has a thickness substantially equal to a thickness of the second gate insulating film;
a fifth gate electrode which is provided over the fifth gate insulating film and has a larger gate length than the second gate electrode;
a fifth source region and a fifth drain region which are provided in the semiconductor substrate respectively on both sides of the fifth gate electrode and contain impurities of the first conductivity type;
a fifth channel region provided in the semiconductor substrate between the fifth source region and the fifth drain region, and
a sixth impurity region which is provided in the semiconductor substrate under the fifth channel region and contains impurities of the second conductivity type in a higher concentration than the fifth channel region.

9. The semiconductor device according to claim 1 , wherein
the first bias and the second bias are equal.

10. A semiconductor device comprising a first transi

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Ema Taiji
• Yasuda Makoto
• Fujita Kazushi

Classifications

• H01L29/105

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L27/088 Primary

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L29/0607

  Electricity · mapped topic