Methods and apparatus for read disturb detection and handling

Patent metadata

Field	Value
Publication number	US-10373695-B2
Application number	US-201615396206-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.

First claim

What is claimed is:

1. A method for use with a non-volatile memory (NVM), the method comprising:
determining a first error level of a first page in a block of the NVM and a second error level of at least one adjacent page having a wordline adjacent to a wordline of the first page occurring over a predetermined number of read accesses of the first page;
determining whether the second error level of the at least one adjacent page is above a first predetermined threshold;
comparing the first error level to the second error level when the second error level is above the first predetermined threshold to determine whether the second error level is greater than the first error level by a predefined factor; and
relocating at least one page within the NVM when the second error level is determined to be greater than the first error level by the predefined factor.

2. The method of claim 1 , wherein the second error level is due, at least in part, to Read Disturb errors, and wherein relocating the at least one page comprises relocating the first page and the at least one adjacent page.

3. The method of claim 2 , further comprising:
establishing a determination of a high error block of the block of the NVM when the second error level is not greater than the first error level by the predefined factor.

4. The method of claim 3 , further comprising:
relocating the at least one adjacent page within the NVM after establishing the high error block.

5. The method of claim 3 , further comprising:
relocating a most significant bit (MSB) and a least significant bit (LSB) address of the at least one adjacent page within the NVM after establishing a high error block.

6. The method of claim 2 , further comprising:
determining a plurality of stages for the first page and the at least one adjacent page based on the determined first and second errors, wherein each of the plurality of stages is a level of severity of the error occurring in a page; and
relocating at least one of a logical block address of the first page, a physical location of the first page and the at least one adjacent page within the NVM, and a block in which the first page and the at least one adjacent page are located based on the stage of the first page and the stage of the at least one adjacent page.

7. The method of claim 6 , further comprising:
maintaining the locations of the first page and the at least one adjacent page when the stage levels of the first page and the least one adjacent page are of values indicating a low level of severity of the error in the pages.

8. The method of claim 6 , wherein the plurality of stages are based on low density parity check (LDPC) decode stages.

9. The method of claim 1 , wherein the NVM comprises NAND-type flash memory.

10. A solid state drive (SSD) comprising:
a non-volatile memory (NVM); and
a controller communicatively coupled to a host device and the NVM,
wherein the controller is configured to:
determine an error level of an aggressor page in the NVM;
determine an error level of a victim page adjacent to the aggressor page within a block of the NVM;
determine whether the error level of the victim page is greater than a first predetermined threshold;
compare the error level of the aggressor page to the error level of the victim page when the error level of the victim is greater than the first predetermined threshold; and
move at least one of the aggressor page and the victim page when the comparison of the error levels of the aggressor and victim pages indicates that victim level error is greater than the first error level by a predefined factor.

11. The solid state drive of claim 10 , wherein the error level of the victim page is due, at least in part, to Read Disturb errors, and the controller is further configured to:
move the aggressor page and the victim page within the NVM after determining the Read Disturb error.

12. The solid state drive of claim 11 , wherein the controller is further configured to move another victim page within the NVM, where the victim page has a wordline number immediately previous to a wordline number of the aggressor page and the another victim page has a wordline number immediately after the wordline number of the aggressor page.

13. The solid state drive of claim 11 , wherein the error level is one of an Error-correcting code (ECC) value and a bit error rate (BER) of a page.

14. The solid state drive of claim 10 , wherein the controller is further configured to establish a determination of a high error block of the block of the NVM when the error level of the victim block is above the first predetermined threshold but is not greater than the error level of the aggressor block by the predefined factor.

15. The solid state drive of claim 14 , wherein the controller is further configured to move a least significant bit (LSB) address and a most significant bit address (MSB) of the victim page within the NVM after determining the high error block.

16. The solid state drive of claim 10 , wherein the controller is further configured to:
assign one of a plurality of error stage values for each of the victim and aggressor pages based on the determined error levels of the victim and aggressor pages, wherein each of the plurality of error stages values represent a level of severity of the error occurring in a page; and
move at least one of a logical block address of the aggressor page, a physical location of the aggressor page and the victim page within the NVM, and an entire block in which the aggressor page and the victim page are located based on the stage of the aggressor page and the stage of the victim page.

17. The solid state drive of claim 16 , wherein the controller is further configured to: maintain the locations of the aggressor and victim pages within the block when the stage levels of the aggressor and victim pages are of values indicating a low level of severity of the error in the pages.

18. The solid state drive of claim 16 , wherein the plurality of error stage values are based on low density parity check (LDPC) decode stages.

19. A memory device for use with a non-volatile memory (NVM), the apparatus comprising:
means for determining whether a number of read accesses of a page in the NVM has reached a predefined value;
means for obtaining an error measure for the page after the number of read accesses has reached the predefined value;
means for obtaining an error measure for at least one neighboring page that is on an adjacent wordline to the page within the NVM;
means for determining if the error measure of the at least one neighboring page is greater than a predefined threshold;
means for relocating the page and the at least one neighboring page when the error measure of the at least one neighboring page is determined to be greater than the error measure of the page by a predefined factor.

20. The memory device of claim 19 , wherein the error measure for the at least one neighboring page is due, at least in part, to a Read Disturb error.

21. The memory device of claim 19 , further comprising:
means for determining a high block error state for a block containing the page and the at least one neighboring page by determining that the error measure of the at least one neighboring page is greater than the predefined value and is not greater than or equal to the error measure of the page by the predefined factor.

22. The memory device of claim 19 , further comprising:
means for relocating the at least one neighbor

Assignees

• Western Digital Tech Inc

Inventors

• Barndt Richard David
• Cometti Aldo Giovanni
• Liu Haining
• Lo Jerry

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title