Display apparatus

Patent metadata

Field	Value
Publication number	US-10373575-B2
Application number	US-201514755241-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Sep 1, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A display apparatus includes: a timing control block which outputs image data based on external image data and control signals, and generates data and gate-side control signals based on the external control signal; a source drive block which converts the image data into a data voltage based on the data control signal; a low frequency detection block which detects a low power drive period based on the external control signal and generates a power control signal, a state of which is determined based on a result of the detection; an integrated chip which receives first and second drive voltages and includes a first switch block that turns off a circuit of the source drive block based on the power control signal during the low power drive period; a gate drive circuit which generates a gate signal based on a gate control signal from the integrated chip; and a display panel.

First claim

What is claimed is:

1. A display apparatus comprising:
a timing control block which outputs image data based on external image data in response to external control signals, and generates a data control signal and a gate-side control signal based on the external control signal;
a source drive block which converts the image data into a data voltage in response to the data control signal;
a low frequency detection block which receives the external control signal, detects a low power drive period based on the external control signal and generates a power control signal, a state of which is determined based on a result of the detection of the low power drive period;
an integrated chip which receives first and second drive voltages, wherein the integrated chip includes a first switch block which turns off a circuit of the source drive block in response to the power control signal from the low frequency detection block during the low power drive period;
a gate drive circuit which generates a gate signal in response to a gate control signal from the integrated chip; and
a display panel which receives the gate signal and the data voltage and displays an image with a frequency higher than a reference frequency in a normal drive mode or with a frequency lower than the reference frequency in a low frequency drive mode,
wherein the power control signal is in the normal drive mode during a plurality of first frame periods corresponding to the frequency higher than the reference frequency,
the power control signal is in the low frequency drive mode during a plurality of second frame periods corresponding to the frequency lower than the reference frequency,
each of the first frame periods includes a first active period during which the data voltage is supplied to the display panel, and a first blank period during which the data voltage is interrupted to the display panel,
each of the second frame periods includes a second active period during which the data voltage is supplied to the display panel, and a second blank period during which the data voltage is interrupted to the display panel,
the second blank period is longer than the first blank period, and
after a beginning and before an end of the second blank period, the gate drive circuit is reset by at least one reset signal.

2. The display apparatus according to claim 1 , wherein the integrated chip further comprises:
a voltage conversion block which receives the first and second drive voltages and outputs a high gate voltage, a low gate voltage and a ground gate voltage; and
a gate control block which receives the gate-side control signal from the timing control block and receives the high and low gate voltages from the voltage conversion block.

3. The display apparatus according to claim 2 , wherein the voltage conversion block comprises:
a first charge pump which converts the first drive voltage into the high gate voltage;
a second charge pump which converts the second drive voltage into the low gate voltage; and
a level adjuster which converts the low gate voltage into the ground gate voltage.

4. The display apparatus according to claim 3 , wherein the first charge pump receives the power control signal from the low frequency detection block and lowers the high gate voltage to the ground gate voltage based on the state of the power control signal during the low power drive period.

5. The display apparatus according to claim 2 , wherein the gate control block comprises:
a control signal generation block which converts the gate-side control signal into the gate control signal, and determines high and low levels of the gate control signal based on the high and low gate voltages from the voltage conversion block; and
a second switch block which receives the power control signal and holds the low gate voltage at the ground gate voltage during the low power drive period.

6. The display apparatus according to claim 2 , wherein the gate control block comprises:
a control signal generation block which converts the gate-side control signal into the gate control signal, and determines high and low levels of the gate control signal based on the high and low gate voltages from the voltage conversion block; and
a second switch block which receives the gate control signal and the low gate signal, and holds the gate control signal and the low gate voltage at the ground gate voltage based on the power control signal from the low frequency detection block during the low power drive period.

7. The display apparatus according to claim 6 , wherein the second switch block comprises:
a first selector which holds the gate control signal at the ground gate voltage in response to the power control signal from the low frequency detection block during the low power drive period; and
a second selector which holds the low gate voltage at the ground gate voltage in response to the power control signal from the low frequency detection block during the low power drive period.

8. The display apparatus according to claim 2 , wherein
the integrated chip is provided in plural,
wherein one of the integrated chips includes the gate control block.

9. The display apparatus according to claim 1 , further comprising:
a voltage conversion block which receives the first and second drive voltages and outputs a high gate voltage, a low gate voltage and a ground gate voltage based on the first and second drive voltages; and
a drive chip including a gate control block which receives the gate-side control signal from the timing control block and receives the high and low gate voltages from the voltage conversion block.

10. The display apparatus according to claim 9 , further comprising:
a printed circuit board on which the drive chip is mounted; and
a connection film which electrically connects the printed circuit board with the display panel.

11. The display apparatus according to claim 9 , wherein
the integrated chip is provided in plural,
wherein one of the integrated chips is electrically connected to the drive chip.

12. The display apparatus according to claim 9 , wherein the voltage conversion block is included in the drive chip.

13. The display apparatus according to claim 1 , wherein the source drive block comprises:
a data converter which converts the image data into data voltages of one line;
an output buffer which stores the data voltages for a predetermined time and outputs the data voltages simultaneously to the display panel; and
a bias current controller which receives the power control signal from the low frequency detection block and controls a bias current that is to be supplied to the output buffer.

14. The display apparatus according to claim 1 , wherein the low power drive period is in the second blank period of each of the second frame periods.

15. The display apparatus according to claim 1 , wherein the timing control block is included in the integrated chip.

16. The display apparatus according to claim 1 , wherein the source drive block is included in the integrated chip.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Suhyeong
• Lee Kyoungwon
• Jung Hoyong
• Park Cheolwoo
• You Bonghyun

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/3685

  Details of drivers for data electrodes · CPC title

• G09G2330/022

  in absence of operation, e.g. no data being entered during a predetermined time · CPC title

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title