Non-volatile storage device system with page based remapping

Patent metadata

Field	Value
Publication number	US-10372341-B2
Application number	US-201715636496-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Jun 28, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A controller addresses portions of non-volatile memory via a memory interface using physical addresses and addresses portions of host data via the host interface using logical addresses. The controller maintains logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses. The controller is configured to move data from a source logical address to a destination logical address by updating logical to physical mappings and physical address to logical mappings without instructing the non-volatile memory to move the data between physical locations. In one embodiment, this process is used to implement a command to move or defragment data.

First claim

What is claimed is:

1. An apparatus, comprising:
a local volatile memory;
a memory structure comprising a plurality of non-volatile memory cells; and
one or more control circuits in communication with the memory structure and the local volatile memory;
in response to a command to move host data from a source logical address to a destination logical address the one or more control circuits are configured to update a logical to physical mapping, update a physical to logical mapping that is stored in the memory cells if the host data is stored in a closed block in the memory cells and update a physical to logical mapping that is stored in the local volatile memory if the host data is stored in an open block in the memory cells, without moving the host data between memory cells.

2. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to read an entry for the source logical address in the logical to physical mappings that identify a physical address in the memory structure storing host data associated with the source logical address; and
the one or more control circuits are configured to update the logical to physical mappings by writing the physical address into an entry for the destination logical addresses in the logical to physical mappings and marking the entry for the source logical addresses in the logical to physical mappings as being invalid.

3. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to update the physical to logical mapping that is stored in the memory cells by appending the destination logical address to the physical to logical mappings stored in the non-volatile memory with an indication of which other logical address to replace without removing the other logical address.

4. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to update the physical to logical mapping that is stored in the memory cells by re-writing the physical to logical mapping that is stored in the memory cells to a new location in the memory cells.

5. The apparatus of claim 1 , wherein:
the physical to logical mapping that is stored in the memory cells is part of a set of management tables stored in separate blocks from the host data.

6. The apparatus of claim 1 , wherein:
the physical to logical mapping that is stored in the memory cells is stored on a different word line than the host data.

7. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to write first data to a first open block of the memory cells, the first data associated with a first logical address, the first open block associated with a first physical address; and
the one or more control circuits are configured to write the first logical address to an entry for the first physical address in the physical to logical mapping that is stored in the local volatile memory.

8. The apparatus of claim 7 , wherein:
the one or more control circuits are configured to write second data to the first open block, the second data associated with a second logical address, the first open block associated with a second physical address, the writing of the second data causes the first open block to become closed; and
in response to the first open block becoming closed, the one or more control circuits are configured to program into the memory cells the physical to logical mapping structure that is stored in the local volatile memory.

9. The apparatus of claim 8 , wherein:
the one or more control circuits are configured to program into the memory cells the physical to logical mapping structure that is stored in the local volatile memory multiple times while the first open block is still an open block.

10. The apparatus of claim 1 , wherein:
the one or more control circuits comprise a controller that includes a host interface, a memory interface configured to communicate with the memory structure and one or more processors in communication with the host interface and the memory interface.

11. The apparatus of claim 10 , wherein:
the controller is configured to address portions of the non-volatile memory via the memory interface using physical addresses, the controller is configured to address portions of host data via the host interface using logical addresses, the controller is configured to maintain logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses.

12. The apparatus of claim 11 , wherein:
logical to physical mappings indicate translations from logical addresses in a logical address space to physical addresses of the memory cells, for entries in logical to physical mappings the logical addresses do not change while the physical addresses do change; and
the physical to logical mapping indicates, for a given physical address, what logical address has its data stored in that physical address, for entries in the physical to logical mapping the physical addresses do not change while the logical addresses do change.

13. A method of operating non-volatile memory, comprising:
receiving one or more commands to move data from source logical addresses to destination logical addresses;
reading entries for the source logical addresses in a set of one or more logical to physical mappings that identify physical addresses in the non-volatile memory that are storing data for the source logical addresses in response to the one or more commands;
writing the physical addresses into entries for the destination logical addresses in the set of one or more logical to physical mappings;
marking the entries for the source logical addresses in the set of one or more logical to physical mappings as being invalid; and
updating entries for the physical addresses in physical to logical mappings to replace source logical addresses with destination logical addresses by updating physical to logical mappings in Controller RAM for open blocks and rewriting physical to logical mappings in the non-volatile memory for closed blocks;

the writing the physical addresses, the marking the entries and the updating entries are performed without physically moving the data represented by the source logical addresses and the destination logical addresses.

14. The method of claim 13 , wherein:
the updating entries for the physical addresses in physical to logical mappings stored in the non-volatile memory comprises adding a destination logical address to the physical to logical mappings stored in the non-volatile memory with an indication of which source logical address to replace without removing the source logical address.

15. The method of claim 13 , wherein:
the updating entries for the physical addresses in physical to logical mappings stored in the non-volatile memory comprises re-writing the physical to logical mappings stored in the non-volatile memory with the destination logical addresses.

16. The method of claim 13 , wherein:
the physical to logical mappings stored in the non-volatile memory are stored in different physical blocks than the data.

17. The method of claim 13 , further comprising:
writing first data to a first open block of the non-volatile memory, the first data associated with a first logical address, the first open block associated with a first physical address; and
writing the first logical address to an entry for the first physical address in a first physical to logical mapping structure in RAM.

18. A method of operating a non-volatile memory system comprising a controller, RAM connected to the controller and

Assignees

• Western Digital Tech Inc

Inventors

• Oshinsky Hadas
• Sela Rotem
• Shaharabany Amir

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title