Method and apparatus for implementing power modes in microcontrollers using power profiles

Patent metadata

Field	Value
Publication number	US-10372184-B2
Application number	US-201615195563-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 28, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A method and apparatus for implementing power modes in microcontrollers (MCUs) using power profiles. In one embodiment of the method, a central processing unit (CPU) of the MCU executes a first instruction for calling a subroutine stored in a memory of the MCU, wherein the first instruction comprises a first parameter to be passed to the subroutine. Thereafter the CPU writes a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter. The MCU operates in a first power mode in response to the CPU writing the first value to the first SFR. The CPU also executes a second instruction for calling the subroutine, wherein the second instruction comprises a second parameter to be passed to the subroutine. In response the CPU writes a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter. The MCU operates in a second power mode in response to the CPU writing the second value to the second SFR. The MCU consumes more power operating in the first power mode than it does when operating in the second power mode.

First claim

What is claimed is:

1. A method implemented in a microcontroller (MCU) that comprises a central processing unit (CPU) and a memory, the method comprising:
the CPU executing a first instruction for activating a function stored in the memory, wherein the first instruction comprises a first parameter to be passed to the function;
the CPU writing a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter;
the MCU operating in a first power mode in response to the CPU writing the first value to the first SFR;
the CPU executing a second instruction for activating the function, wherein the second instruction comprises a second parameter to be passed to the function;
the CPU writing a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter;
the MCU operating in a second power mode in response to the CPU writing the second value to the second SFR;
wherein the MCU consumes more power operating in the first power mode than it does when operating in the second power mode;
the CPU, in response to executing the first instruction, accessing a data structure stored in the memory to read a plurality of first values that are mapped to the first parameter, wherein the first value is one of the plurality of first values;
the CPU writing the plurality of first values to a plurality of first SFRs, respectively, of the MCU, wherein the first SFR is one of the plurality of first SFRs;
the CPU, in response to executing the second instruction, accessing the data structure stored in the memory to read a plurality of second values that are mapped to the second parameter, wherein the second value is one of the plurality of second values;
the CPU writing the plurality of second values to a plurality of second SFRs, respectively, of the MCU, wherein the second SFR is one of the plurality of second SFRs;
wherein at least one SFR is shared between the plurality of first SFRs and the plurality of second SFRs.

2. The method of claim 1 wherein the data structure maps a plurality of parameters to a plurality of values, respectively, wherein the data structure was created using a graphical user interface before the data structure is written to the memory.

3. A memory storing instructions wherein a method is implemented in response to executing the instructions, the method comprising:
a CPU writing a first value to a first special function register (SFR) of an MCU in response to executing a first instruction that comprises a first parameter, wherein the first value is related to the first parameter;
the CPU writing a second value to a second SFR of the MCU in response to executing the second instruction comprising a second parameter, wherein the second value is related to the second parameter;
wherein the MCU is configured to operate in a first power mode in response to the CPU writing the first value to the first SFR;
wherein the MCU is configured to operate in a second power mode in response to the CPU writing the second value to the second SFR;
wherein the MCU consumes more power when operating in the first power mode than it does when operating in the second power mode;
the CPU, in response to executing the first instruction, accessing a data structure stored in a memory of the MCU to read a plurality of first values that are mapped to the first parameter, wherein the first value is one of the plurality of first values;
the CPU writing the plurality of first values to a plurality of first SFRs, respectively, of the MCU, wherein the first SFR is one of the plurality of first SFRs;
the CPU, in response to executing the second instruction, accessing the data structure to read a plurality of second values that are mapped to the second parameter,
wherein the second value is one of the plurality of second values;
the CPU writing the plurality of second values to a plurality of second SFRs, respectively, of the MCU, wherein the second SFR is one of the plurality of second SFRs;
wherein at least one SFR is shared between the plurality of first SFRs and the plurality of second SFRs.

4. The memory of claim 3 wherein the data structure maps a plurality of parameters to a plurality of values, respectively, wherein the data structure was created using a graphical user interface before the data structure is written to the memory of the MCU.

Assignees

• Renesas Electronics America Inc

Inventors

• Sparling Dale

Classifications

• G06F9/30083

  Power or thermal control instructions · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title