Factory reset apparatus and method

Patent metadata

Field	Value
Publication number	US-10372180-B2
Application number	US-201816013954-A
Country	US
Kind code	B2
Filing date	Jun 21, 2018
Priority date	Dec 21, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal.

First claim

What is claimed is:

1. A factory reset apparatus, comprising a reset switch, a first power supply module, a flip-flop, and a processor, wherein the flip-flop comprises a data input pin, a clock pin, and a true flip-flop output pin, wherein
the reset switch is connected to the data input pin;
the first power supply module is connected to the clock pin; and
the true flip-flop output pin is connected to a first general purpose input/output (GPIO) pin of the processor; and, wherein
the reset switch is configured to generate a low-level reset signal when being pressed, wherein the low-level reset signal is input into the flip-flop from the data input pin;
the flip-flop is configured to receive an electrical signal from the clock pin, wherein a rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the low-level reset signal;
the flip-flop is configured to output a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the low-level reset signal; and
the processor is configured to start a factory reset operation according to a reset request signal input from the first GPIO pin.

2. The apparatus according to claim 1 , wherein the first power supply module is further connected to a power input pin and a ground pin of the flip-flop;
the first power supply module is configured to supply, after being powered on, working power to the flip-flop; and
the apparatus further comprises a delay circuit, wherein
the first power supply module is connected to the clock pin by using the delay circuit; and
an original signal that is output by the first power supply module when being powered on passes through the delay circuit and is output as the electrical signal.

3. The apparatus according to claim 1 , further comprising a second power supply module, wherein
the second power supply module is connected to a power input pin and a ground pin of the flip-flop, and the second power supply module supplies, after being powered on, working power to the flip-flop;
the second power supply module is powered on earlier than the first power supply module; and
the first power supply module outputs the electrical signal when being powered on.

4. The apparatus according to claim 1 , wherein the flip-flop further comprises a preset pin, and the preset pin is connected to a second GPIO pin of the processor;
the processor is further configured to: after starting the factory reset operation according to the low-level reset request signal, output a reset control signal by using the second GPIO pin, wherein the reset control signal is input into the flip-flop from the preset pin; and
the flip-flop performs a reset operation according to the reset control signal.

5. The apparatus according to claim 4 , wherein the reset control signal is a low-level signal, and a low-level reset control signal is input into the flip-flop from the preset pin, so that the true flip-flop output pin of the flip-flop outputs a high-level signal.

6. The apparatus according to claim 4 , wherein the flip-flop is further configured to determine, according to the reset control signal input from the preset pin, that the second GPIO pin is in a high-impedance state, so that a level of the preset pin is pulled up to a power supply level by using a pull-up resistor.

7. A factory reset method, wherein the method is applied to a factory reset apparatus, and the factory reset apparatus comprises a reset switch, a first power supply module, a flip-flop, and a processor, wherein the flip-flop comprises a data input pin, a clock pin, and a true flip-flop output pin, wherein
the reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to a first general purpose input/output (GPIO) pin of the processor; and, wherein
the method comprises:
generating, by the reset switch, a low-level reset signal when being pressed, wherein the low-level reset signal is input into the flip-flop from the data input pin;
receiving, by the flip-flop, an electrical signal from the clock pin, wherein a rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the low-level reset signal;
outputting, by the flip-flop, a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the low-level reset signal; and
starting, by the processor, a factory reset operation according to a reset request signal input from the first GPIO pin.

8. The method according to claim 7 , wherein the factory reset apparatus further comprises a delay circuit, the first power supply module is connected to the clock pin by using the delay circuit, and the first power supply module is further connected to a power input pin and a ground pin of the flip-flop; and
before the receiving, by the flip-flop, an electrical signal from the clock pin, the method further comprises:
supplying, by the first power supply module after being powered on, working power to the flip-flop by using the power input pin and the ground pin of the flip-flop; and
outputting, by the first power supply module when being powered on, an original signal to the delay circuit, wherein the original signal passes through the delay circuit and is output as the electrical signal.

9. The method according to claim 7 , wherein the factory reset apparatus further comprises a second power supply module, the second power supply module is connected to a power input pin and a ground pin of the flip-flop, and the second power supply module is powered on earlier than the first power supply module; and
before the receiving, by the flip-flop, an electrical signal from the clock pin, the method further comprises:
supplying, by the second power supply module after being powered on, working power to the flip-flop; and
outputting, by the first power supply module, the electrical signal when being powered on.

10. The method according to claim 7 , wherein the flip-flop further comprises a preset pin, and the preset pin is connected to a second GPIO pin of the processor; and
the method further comprises:
after the processor starts the factory reset operation according to the low-level reset request signal, outputting, by the processor, a reset control signal by using the second GPIO pin, wherein the reset control signal is input into the flip-flop from the preset pin; and
performing, by the flip-flop, a reset operation according to the reset control signal.

11. The method according to claim 10 , further comprising:
pulling the preset pin to a high-level state by using a pull-up resistor when the second GPIO pin is in a high-impedance state.

12. The method according to claim 8 , wherein the factory reset apparatus further comprises an edge steep circuit, the method further comprises:
increasing a steepness of a rising edge of the electrical signal by using the edge steep circuit.

13. The apparatus according to claim 2 , further comprising:
an edge steep circuit connected to the delay circuit and configured to increase a steepness of a rising edge of the electrical signal.

14. The apparatus according to claim 3 , wherein the flip-flop further comprises a clear pin connected to the second power supply module.

15. The apparatus according to claim 4 , wherein the flip-flop further comprises a pull-up resistor configured to pull the preset pin to a high-level state when the second GPIO pin is in a high-impedance state.

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhang Ruhong
• Ding Jinbo
• Xie Zhengsheng

Classifications

• H03K3/356

  Bistable circuits · CPC title

• G06F1/24 Primary

  Resetting means · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title