Array substrate and method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-10372000-B2
Application number	US-201615531294-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	Mar 31, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

There is disclosed a method of manufacturing an array substrate, the method including a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors on the substrate includes: forming a first electrically conductive layer on the substrate; forming an insulating layer on the first electrically conductive layer; forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer; forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer. In addition, there is disclosed an array substrate manufactured by the above method and a display device including the array substrate.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, the method comprising a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors on the substrate comprises:
forming a first electrically conductive layer on the substrate;
forming an insulating layer on the first electrically conductive layer;
forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer;
forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer, wherein the first electrically conductive layer includes a common electrode pattern and a gate pattern of the thin film transistors, and the second electrically conductive layer includes a source electrode pattern and a drain electrode pattern of the thin film transistors and leading wires thereof,
the step of forming the first connection portion, which is made of the same material as the second electrically conductive layer, in at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer comprises:
forming the source electrode pattern and the drain electrode pattern of the thin film transistors and the leading wires thereof from metal material while forming the first connection portion in the at least one common holes from the metal material, the first connection portion being in electrical contact with the common electrode pattern.

2. The method according to claim 1 , wherein the insulating layer comprises a gate insulating layer, or comprises a gate insulating layer and an etch barrier layer,
the step of forming the at least one common holes in the insulating layer to communicate with the first electrically conductive layer comprises:
forming an active layer pattern at a location, corresponding to the gate pattern, on the gate insulating layer;
forming the etch barrier layer on the substrate obtained;
forming at least one common holes, at locations of the etch barrier layer corresponding to the common electrode pattern, the at least one common holes being communicated with the common electrode pattern.

3. The method according to claim 1 further comprising steps of:
forming a passivation layer on the second electrically conductive layer, the passivation layer covering the first connection portion;
etching a portion of the passivation layer corresponding to the first connection portion to expose the first connection portion; and
forming at least one common electrode connection lines on the passivation layer, the common electrode connection lines each being in electrical connection with the first connection portion in the at least one common holes.

4. A method of manufacturing an array substrate, the method comprising a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors On the substrate comprise:
forming a first electrically conductive layer on the substrate;
forming an insulating layer on the first electrically conductive layer;
forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer;
forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer, wherein the first electrically conductive layer comprises the source electrode pattern and the drain electrode pattern of the thin film transistors and the leading wires thereof, and the second electrically conductive layer comprises a gate pattern of the thin film transistors,
the step of forming the first connection portion, which is made of the same material as the second electrically conductive layer, in at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer comprises:
forming the first connection portion from the metal material in at least one of the at least one common holes while forming the gate pattern of the thin film transistors from the metal material, the first connection portion being in electrical contact with one of the source electrode pattern and the drain electrode pattern of the thin film transistors.

5. The method according to claim 4 , further comprising a step of: forming a second connection portion from the same material as the second electrically conductive layer in the rest of the at least one common holes while forming the second electrically conductive layer on the insulating layer.

6. The method according to claim 5 , wherein the step of forming the second connection portion from the same material as the second electrically conductive layer in the rest of the at least one common holes while forming the second electrically conductive layer on the insulating layer comprises:
forming the second connection portion from the metal material in the rest of the at least one common holes while forming the gate pattern of the thin film transistors from the metal material, the second connection portion being in electrical contact with the other of the source electrode pattern and the drain electrode pattern.

7. The method according to claim 4 , wherein the insulating layer comprises a gate insulating layer,
the step of forming the at least one common holes in the insulating layer to communicate with the first electrically conductive layer comprises:
forming the at least one common holes at locations of the gate insulating layer corresponding to the source electrode pattern and the drain electrode pattern to communicate with the source electrode pattern and the drain electrode pattern of the thin film transistors.

8. The method according to claim 7 , further comprising:
forming a passivation layer on the second electrically conductive layer, the passivation layer covering the first connection portion;
etching and removing a portion of the passivation layer corresponding to the first connection portion to expose the first connection portion; and
forming a pixel electrode pattern and/or a data line pattern, which are respectively in electrical connection with the drain electrode pattern and/or the source electrode pattern of the thin film transistors through the common holes and the first connection portion in the common holes, on the passivation layer.

9. The method according to claim 8 , wherein the pixel electrode pattern and the data line pattern are formed on the passivation layer and are respectively in electrical connection with the drain electrode pattern and the source electrode pattern through the common holes and the first connection portion and the second connection portion in the common holes.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Song Botao
• Lin Liang
• Ma Tao
• Wang Wenlong
• Han Ling
• Wei Yu

Classifications

• G02F1/134336

  Matrix · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2001/13685

  Physics · mapped topic

• G02F2001/136295

  Physics · mapped topic

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title