Systems and methods for optical distance measurement

Patent metadata

Field	Value
Publication number	US-10371802-B2
Application number	US-201815944729-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Jul 20, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Systems and methods for performing optical distance measurement are provided. In one aspect, a system for measuring a distance to an object comprises a light emitter configured to emit an outbound light pulse, and a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse. The system also comprises a field-programmable gate array (FPGA) coupled to the light sensor. The FPGA is configured to convert the analog pulse signal to a plurality of digital signal values, and generate a plurality of time measurements corresponding to the plurality of digital signal values. The system also comprises a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.

First claim

We claim:

1. A system for measuring a distance to an object, the system comprising:
a light emitter configured to emit an outbound light pulse;
a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse;
a field-programmable gate array (FPGA) coupled to the light sensor, wherein the FPGA includes a plurality of delay units and a plurality of latches, wherein the delay units are sequentially coupled to each other, wherein each latch is coupled to a corresponding delay unit of the plurality of delay units, and wherein the FPGA is configured to—
convert the analog pulse signal to a plurality of digital signal values, and
generate a plurality of time measurements corresponding to the plurality of digital signal values by sampling each digital signal value, wherein a time resolution of the sampling is shorter than a clock period of the FPGA, and wherein sampling each digital signal value includes—
transmitting the digital signal value sequentially along the plurality of delay units;
determining a number of the plurality of latches that were triggered during a clock cycle of the FPGA, wherein each latch is configured to be latched in response to the corresponding delay unit receiving the digital signal value; and
calculating a time measurement corresponding to the digital signal value based on the determined number; and

a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.

2. The system of claim 1 , wherein the light emitter, light sensor, FPGA, and controller are carried by an unmanned vehicle, an autonomous vehicle, or a robot.

3. The system of claim 1 , wherein the time resolution is at least 5 times shorter than the clock period of the FPGA.

4. The system of claim 1 , wherein the plurality of delay units comprises at least 25 delay units.

5. The system of claim 1 , wherein the plurality of delay units comprises a carry chain or a lookup table (LUT).

6. The system of claim 1 , wherein each of the plurality of delay units is configured to produce a delay within a range from 5 picoseconds to 2000 picoseconds.

7. The system of claim 1 , further comprising a temperature sensor positioned on, in, or near the FPGA, wherein the FPGA is configured to generate the plurality of time measurements by:
receiving a temperature value from the temperature sensor; and
calculating the time measurement based on the temperature value.

8. The system of claim 1 wherein the field-programmable gate array (FPGA) is configured to convert the analog pulse signal to the plurality of digital signal values by (1) comparing the analog pulse signal to a plurality of threshold values and (2) generating the plurality of digital signal values based on the comparison.

9. The system of claim 8 , wherein the plurality of different threshold values comprises at least 2 different threshold values.

10. The system of claim 8 , wherein the FPGA comprises a plurality of differential input ports, and wherein the FPGA is configured to convert the analog pulse signal using the plurality of differential input ports.

11. The system of claim 10 , wherein each differential input port comprises a low-voltage differential signaling (LVDS) interface or an emitter-coupled logic (ECL) interface.

12. The system of claim 10 , wherein the FPGA is further configured to: receive the analog pulse signal and a threshold value at each of the plurality of differential input ports, wherein each differential input port receives a different threshold value.

13. The system of claim 8 , wherein the controller is configured to calculate the distance by:
inputting the plurality of digital signal values and the plurality of time measurements into a function; and
deriving an estimated time value for the returning light pulse using the function.

14. The system of claim 13 , wherein the function comprises a pulse signal model, and wherein the estimated time value is derived by fitting the plurality of digital signal values and the plurality of time measurements to the pulse signal model.

15. A method for measuring a distance to an object, the method comprising:
emitting, by a light emitter, an outbound light pulse;
receiving, at a light sensor, a returning light pulse reflected from the object;
outputting, by the light sensor, an analog pulse signal representing the returning light pulse;
converting, using a field-programmable gate array (FPGA), the analog pulse signal to a plurality of digital signal values;
generating, using the FPGA, a plurality of time measurements corresponding to the plurality of digital signal values by sampling each digital signal value, wherein a time resolution of the sampling is shorter than a clock period of the FPGA, and wherein sampling each digital signal value includes—
transmitting the digital signal value along a plurality of sequentially coupled delay units;
determining a number of a plurality of latches that were triggered during a clock cycle of the FPGA, wherein each latch is coupled to a corresponding delay unit of the plurality of delay units, and wherein each latch is configured to be latched in response to the corresponding delay unit receiving the digital signal value; and
calculating a time measurement corresponding to the digital signal value based on the determined number; and

calculating the distance to the object based on the plurality of digital signal values and the plurality of time measurements.

16. The method of claim 15 , wherein the light emitter, light sensor, and FPGA are carried by an unmanned vehicle, an autonomous vehicle, or a robot.

17. The method of claim 15 , wherein generating the plurality of time measurements comprises:
receiving a temperature value from a temperature sensor positioned on, in, or near the FPGA; and
calculating the time measurement based on the temperature value.

18. The method of claim 15 wherein converting the analog pulse signal to the plurality of digital signal values includes (1) comparing the analog pulse value to a plurality of threshold values and (2) generating the plurality of digital signal values based on the comparison.

19. The method of claim 18 , wherein the FPGA comprises a plurality of differential input ports, and wherein the converting step is performed using the plurality of differential input ports.

20. The method of claim 19 , further comprising: receiving the analog pulse signal and a threshold value at each of the plurality of differential input ports, wherein each differential input port receives a different threshold value.

21. The method of claim 20 , wherein the analog pulse signal is received at a first pin of each differential input port and the threshold value is received at a second pin of each differential input port.

22. The method of claim 21 , further comprising applying an adjustment voltage to the second pin of each differential input port, wherein the adjustment voltage is configured to compensate for an offset voltage between the first and second pins of the differential input port.

Assignees

• Sz Dji Technology Co Ltd

Inventors

• Liu Xiang
• Gao Mingming
• Hong Xiaoping
• Wu Di

Classifications

• G01S7/4861 Primary

  Circuits for detection, sampling, integration or read-out · CPC title

• G01S17/10 Primary

  using transmission of interrupted, pulse-modulated waves (determination of distance by phase measurements G01S17/32) · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03K19/017581

  programmable · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title