Rate determination apparatus, rate determination method, and reception apparatus

Patent metadata

Field	Value
Publication number	US-10367660-B2
Application number	US-201715801394-A
Country	US
Kind code	B2
Filing date	Nov 2, 2017
Priority date	Dec 14, 2016
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.

First claim

What is claimed is:

1. A rate determination apparatus comprising:
a memory for storing instructions; and
a processor configured to execute the stored instructions to implement:
a receiver configured to receive a transmission frame modulated by a Frequency Shift Keying (FSK) modulation scheme;
a symbol rate detector configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame;
a multilevel symbol detector configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame; and
a bit rate determiner configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol, wherein

the multilevel symbol detector detects the multilevel symbol based on a difference between a specific frequency deviation pattern corresponding to the multilevel symbol to be detected and a reception frequency deviation in the transmission frame,
the multilevel symbol detector detects the multilevel symbol based on an average of the difference between the specific frequency deviation pattern and the reception frequency deviation,
the specific frequency deviation pattern includes a plurality of frequency deviation routes corresponding to combinations of frequencies between symbols, and
the multilevel symbol detector detects the multilevel symbol based on a frequency deviation route having a smallest average of the difference from the reception frequency deviation among the plurality of frequency deviation routes.

2. A rate determination apparatus comprising:
a memory for storing instructions; and
a processor configured to execute the stored instructions to implement:
a receiver configured to receive a transmission frame modulated by a Frequency Shift Keying (FSK) modulation scheme;
a symbol rate detector configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame;
a multilevel symbol detector configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame; and
a bit rate determiner configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol, wherein

the multilevel symbol detector detects the multilevel symbol based on a difference between a specific frequency deviation pattern corresponding to the multilevel symbol to be detected and a reception frequency deviation in the transmission frame or a result of a hard decision on the frequency deviation in the transmission frame,
the multilevel symbol detector detects the multilevel symbol according to the difference or the result of the hard decision according to received signal strength of the transmission frame, and
when the received signal strength is lower than a threshold, the multilevel symbol detector detects the multilevel symbol based on the difference, while when the received signal strength is greater than the threshold, the multilevel symbol detector detects the multilevel symbol based on the result of the hard decision.

3. A rate determination apparatus comprising:
a memory for storing instructions; and
a processor configured to execute the stored instructions to implement:
a receiver configured to receive a transmission frame modulated by a Frequency Shift Keying (FSK) modulation scheme;
a symbol rate detector configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame;
a multilevel symbol detector configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame; and
a bit rate determiner configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol, wherein

the symbol rate detector detects the symbol rate based on a zero-crossing point in a frequency deviation in the preamble portion or a cross-correlation value with a predetermined periodic pattern of the preamble portion,
the symbol rate detector detects the symbol rate based on the zero-crossing point or the cross-correlation value according to received signal strength of the transmission frame, and
when the received signal strength is lower than a threshold, the symbol rate detector detects the symbol rate based on the cross-correlation value, while when the received signal strength is greater than the threshold, the symbol rate detector detects the symbol rate based on the zero-crossing point.

Assignees

• Renesas Electronics Corp

Inventors

• Kim Kichung
• Okada Hiroyuki
• Matsui Naohiro
• Hirota Tomoaki

Classifications

• H04L27/14

  Demodulator circuits; Receiver circuits · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L25/0262 Primary

  Arrangements for detecting the data rate of an incoming signal · CPC title

• H04L1/0038

  Blind format detection (for detection of modulation format H04L27/0012) · CPC title

• H04L7/00

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title