Apparatus and system for generating a signal with phase angle configuration

Patent metadata

Field	Value
Publication number	US-10367409-B2
Application number	US-201715402021-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Dec 23, 2011
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

First claim

We claim:

1. An apparatus comprising:
a delay line having a plurality of delay elements to provide control signals, the plurality of delay elements comprising
a first delay element;
a second delay element; and
a third delay element coupled in series to the first delay element and the second delay element, wherein the first delay element comprises:
a first differential delay cell to output a first output signal to the second delay element; and
a second differential delay cell to receive the first output signal from the first differential delay cell, the second differential delay cell to generate the control signals;
an array of switch-resistors comprising first inputs to receive the control signals, a second input coupled to the first inputs, and an output coupled to the first inputs to generate an output signal, wherein the second input of the array is configured to receive a phase change signal to adjust a phase angle of the output signal by enabling or disabling a row or a column of the switch-resistors of the array according to the phase angle.

2. The apparatus of claim 1 , wherein the first and second differential delay cells have identical designs.

3. The apparatus of claim 1 , wherein the first differential delay cell is coupled to a varactor.

4. The apparatus of claim 3 , wherein the varactor comprises:
a first transistor including:
a gate terminal coupled to a node having a tunable signal;

a drain terminal coupled to a node having the first output signal from the first differential delay cell; and a source terminal coupled to another transistor.

5. The apparatus of claim 1 , wherein the first differential cell comprises:
a first p-type transistor to provide a current according to a first bias voltage applied at its gate terminal; and a p-differential cascode pair including:
a second p-type transistor to receive an input signal; and
a third p-type transistor cascoded with the second p-type transistor, the third p-transistor to receive the first bias voltage at its gate terminal.

6. The apparatus of claim 5 , wherein the third p-transistor has a drain/source terminal coupled to a first output node carrying the first output signal.

7. The apparatus of claim 5 , wherein the p-differential cascode pair comprises: a fourth p-type transistor to receive a complementary signal which is complementary of the input signal; and a fifth p-type transistor cascoded with the fourth p-type transistor, the fifth p-transistor to receive the first bias voltage at its gate terminal.

8. The apparatus of claim 5 , wherein the fifth p-transistor has a drain/source terminal coupled to a second output node carrying a complementary signal which is complementary to the first output signal.

9. The apparatus of claim 5 further comprises:
a second n-type transistor coupled with the drain/source terminal of the first p-type transistor; and a third n-type transistor coupled in series with the second n-type transistor.

10. The apparatus of claim 9 further comprises:
a fourth n-type transistor coupled with the drain/source terminal of the first p-type transistor; and a fifth n-type transistor coupled in series with the fourth n-type transistor.

11. The apparatus of claim 1 , wherein the first differential cell comprises:
a first n-type transistor to provide a current according to a second bias voltage applied at its gate terminal.

12. The apparatus of claim 11 , wherein the first differential cell comprises: an n-differential cascode pair including: a seventh n-type transistor to receive an input signal; and a sixth n-type transistor cascoded with the seventh p-type transistor, the sixth p-transistor to receive the second bias voltage at its gate terminal.

13. An apparatus comprising:
an array of switch-resistors, each switch-resistor of the array to receive control signals from a delay line, wherein the array of switch-resistors is to generate an output signal, and wherein the array of switch-resistors comprises a switch-resistor core to receive the control signals and a circuit to output first signals other than the control signals to the switch resistor core to adjust a phase angle of the output signal by enabling or disabling a row or a column of the switch-resistors of the array according to the phase angle.

14. The apparatus of claim 13 , wherein each switch-resistor comprises:
a first switch coupled to a first power supply; a second switch coupled to a second power supply and coupled in series with the first switch; and a resistor coupled to the first and second switches and a node carrying the output signal.

15. The apparatus of claim 14 , wherein the first and second switches are transistors which are operable to receive the control signals at their gate terminals.

16. The apparatus of claim 13 , wherein each switch-resistor comprises:
a first resistor-switch coupled to a first power supply; and a second resistor-switch coupled to a second power supply and coupled in series with the first resistor-switch, wherein the first and second resistor-switches are coupled to a node carrying the output signal.

17. The apparatus of claim 16 , further comprising: a resistor coupled to the first and second resistor-switches and a carrying the output signal.

18. The apparatus of claim 16 , wherein each of the first and second resistor-switches comprises: a transistor which is operable to receive a control signal at its gate terminal.

Assignees

• Intel Corp

Inventors

• Schrom Gerhard
• Raghuraman Narayanan
• Paillet Fabrice

Classifications

• H02M2003/1586

  Electricity · mapped topic

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03H7/325 Primary

  Adjustable networks · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title