Display panel and display device

Patent metadata

Field	Value
Publication number	US-10367052-B2
Application number	US-201816161081-A
Country	US
Kind code	B2
Filing date	Oct 16, 2018
Priority date	Jun 26, 2018
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A display panel and a display device are provided. A display region is divided into a first display region and at least one second display region smaller than the first display region. The display panel includes compensation lines and to-be-compensated lines located in the display region. Each compensation line is electronically connected with one to-be-compensated line, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one power supply line on the substrate, and a capacitance is formed between the compensation line and the power supply line, or each compensation line is electronically connected with one power supply line, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one to-be-compensated line on the substrate, and a capacitance is formed between the compensation line and the to-be-compensated line.

First claim

The invention claimed is:

1. A display panel, comprising:
a substrate;
a display region, and a non-display region surrounding the display region, wherein the display region is divided into a first display region and at least one second display region smaller than the first display region;
a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer which are sequentially arranged in a direction away from the substrate;
a plurality of gate lines extending in a first direction and arranged in a second direction, a plurality of data lines arranged in the first direction and extending in the second direction, and a plurality of power supply lines arranged in the first direction and extending in the second direction, which are arranged above the substrate, wherein the first direction intersects the second direction, the plurality of gate lines is located on the first metal layer, the plurality of data lines and the plurality of power supply lines are located on the second metal layer, the plurality of gate lines comprises first gate lines and second gate lines shorter than the first gate lines, the plurality of data lines comprises first data lines and second data lines shorter than the first data lines, the first gate lines are located in the first display region, the second gate lines are located in the second display region; and
a plurality of compensation lines and to-be-compensated lines located in the display region, wherein each of the to-be-compensated lines is one of the second gate lines or one of the second data lines, and the plurality of compensation lines is located on the third metal layer, wherein
each of the plurality of compensation lines is electronically connected with one of the to-be-compensated lines, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one of the plurality of power supply lines on the substrate, and a capacitance is formed between the compensation line and the power supply line; or
each of the plurality of compensation lines is electronically connected with one of the plurality of power supply lines, an orthographic projection of the compensation line on the substrate is overlapped with an orthographic projection of one of the to-be-compensated lines on the substrate, and a capacitance is formed between the compensation line and the to-be-compensated line.

2. The display panel according to claim 1 , wherein in the case that a capacitance is formed between the compensation line and the power supply line, an extension direction of the compensation line is the same as an extension direction of the power supply line.

3. The display panel according to claim 2 , wherein each of the to-be-compensated lines is electronically connected with one or more compensation lines among the plurality of compensation lines.

4. The display panel according to claim 3 , wherein at least one of the compensation lines is electronically connected with the to-be-compensated line through a first via hole.

5. The display panel according to claim 4 , wherein the first via hole is a first A via hole located on the first insulating layer and the second insulating layer, or a first B via hole located on the second insulating layer; wherein
in a case that the to-be-compensated line is the second gate line, the compensation line is electronically connected with the second gate line via the first A via hole;
in a case that the to-be-compensated line is the second data line, the compensation line is electronically connected with the second gate line via the first B via hole.

6. The display panel according to claim 3 , wherein at least one of the compensation lines is electronically connected with the to-be-compensated line through a first connection lead, and the first connection lead is located in the non-display region.

7. The display panel according to claim 6 , wherein in a case that the to-be-compensated line is the second gate line,
the first connection lead and the second gate line are arranged on a same layer, and the first connection lead is electronically connected with the compensation line through a second A via hole located on the first insulating layer and the second insulating layer; or
the first connection lead and the compensation line are arranged on a same layer, and the first connection lead is electronically connected with the second gate line through a second B via hole located on the first insulating layer and the second insulating layer,
wherein in a case that the to-be-compensated line is the second data line,
the first connection lead and the second data line are arranged on a same layer, and the first connection lead is electronically connected with the compensation line through a third A via hole located on the second insulating layer; or
the first connection lead and the compensation line are arranged on a same layer, and the first connection lead is electronically connected with the second data line through a third B via hole located on the second insulating layer.

8. The display panel according to claim 1 , wherein in the case that a capacitance is formed between the compensation line and the to-be-compensated line, an extension direction of the compensation line is the same as an extension direction of the to-be-compensated line.

9. The display panel according to claim 8 , wherein in the display region, an orthographic projection of each of the to-be-compensated lines on the substrate is overlapped with an orthographic projection of one of the plurality of compensation lines on the substrate.

10. The display panel according to claim 8 , wherein in the display region, an orthographic projection of each of the to-be-compensated lines on the substrate is overlapped with orthographic projections of segmented compensation lines among the plurality of compensation lines on the substrate.

11. The display panel according to claim 1 , wherein the display region is provided with a plurality of pixel unit rows arranged in the second direction, each of the plurality of pixel unit rows comprises a plurality of sub-pixel units each defined by adjacent data lines among the plurality of data lines and adjacent gate lines among the plurality of gate lines, wherein
in the second display region, the number of sub-pixel units in a pixel unit row close to the first display region among the plurality of pixel unit rows is greater than the number of sub-pixel units in a pixel unit row away from the first display region among the plurality of pixel unit rows.

12. The display panel according to claim 11 , wherein in a case that the to-be-compensated line is the second gate line,
an overlapping area between orthographic projections of the compensation line and the power supply line corresponding to the pixel unit row close to the first display region on the substrate is less than an overlapping area between orthographic projections of the compensation line and the power supply line corresponding to the pixel unit row away from the first display region on the substrate; or
an overlapping area between orthographic projections of the compensation line and the second gate line corresponding to the pixel unit row close to the first display region on the substrate is less than an overlapping area between orthographic projections of the compensation line and the second gate line corresponding to the pixel unit row away from the first display region on the substrate.

13. The display panel according to claim 12 , wherein a width of the compensation line corresponding to the pixel unit row close to the first display region is less t

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Zhang Chunpeng
• Li Bo
• Ma Yangzhao

Classifications

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• H01L27/3276 Primary

  Electricity · mapped topic

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title