Semiconductor optical integrated circuit

US10365507B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10365507-B2
Application numberUS-201815977050-A
CountryUS
Kind codeB2
Filing dateMay 11, 2018
Priority dateMay 26, 2017
Publication dateJul 30, 2019
Grant dateJul 30, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a semiconductor optical integrated circuit which consumes less electric power than a conventional semiconductor optical integrated circuit. A semiconductor optical integrated circuit ( 1 ) includes a semiconductor layer ( 13 ) in which (i) an optical waveguide (LG) including heated section I 1 through I 3 and (ii) heater parts H 1 and H 2 are provided. The optical waveguide (LG) meanders such that the heated sections I 1 through I 3 are juxtaposed to one another. Each heater part Hi is arranged between a heated section Ii and a heated section Ii+1 which are adjacent to each other.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor optical integrated circuit, comprising: a semiconductor layer in which an optical waveguide is provided, the optical waveguide including n heated sections I 1 through In, where n is a natural number of not less than 2; and (n+1) heater parts H 0 through Hn configured to heat the heated sections I 1 through In, the optical waveguide being configured to meander such that the heated sections I 1 through In are juxtaposed to each other, and each heated section Ii (where i=1, 2, . . . , n) being arranged between a heater part Hi−1 and a heater part Hi which are adjacent to each other. 2. The semiconductor optical integrated circuit as set forth in claim 1 , wherein the optical waveguide and the heater parts H 0 through Hn are provided on a same surface. 3. The semiconductor optical integrated circuit as set forth in claim 1 , wherein the heater parts H 0 through Hn are regions of the semiconductor layer to which regions a dopant is injected. 4. The semiconductor optical integrated circuit as set forth in claim 1 , wherein a common voltage is applied across the heater parts H 0 through Hn. 5. The semiconductor optical integrated circuit as set forth in claim 1 , wherein a center-to-center distance between the heated section Ii and the heated section Ii+1, which are adjacent to each other, is not more than 4 μm. 6. The semiconductor optical integrated circuit as set forth in claim 1 , wherein the semiconductor layer is made of silicon. 7. A semiconductor optical integrated circuit, comprising: a semiconductor layer in which an optical waveguide is provided, the optical waveguide including n heated sections I 1 through In, where n is a natural number of not less than 2; and (n−1) heater parts H 1 through Hn−1 configured to heat the heated sections I 1 through In, the optical waveguide being configured to meander such that the heated sections I 1 through In are juxtaposed to each other, each heater part Hi (where i=1, 2, . . . , n−1) being arranged between a heated section Ii and a heated section Ii+1 which are adjacent to each other, the optical waveguide being composed of a rib part and slab parts, the rib part being relatively tall and being located in a center of the optical waveguide, the slab parts being relatively short and being located at respective both ends of the optical waveguide, and a same surface is formed by (i) an upper surface of each heater part Hi (where i=1, 2, . . . , n−1) and (ii) an upper surface of each of the slab parts. 8. The semiconductor optical integrated circuit as set forth in claim 7 , wherein the optical waveguide and the heater parts H 1 through Hn−1 are provided on a same surface. 9. The semiconductor optical integrated circuit as set forth in claim 7 , wherein the heater parts H 1 through Hn−1 are regions of the semiconductor layer to which regions a dopant is injected. 10. The semiconductor optical integrated circuit as set forth in claim 7 , wherein a common voltage is applied across the heater parts H 1 through Hn−1. 11. The semiconductor optical integrated circuit as set forth in claim 7 , wherein a center-to-center distance between the heated section Ii and the heated section Ii+1, which are adjacent to each other, is not more than 4 μm. 12. A semiconductor optical integrated circuit as set forth in claim 7 , further comprising: a heater part H 0 ; and a heater part Hn, each heated section Ij (where j=1, 2, . . . , n) being arranged between a heater part Hj−1 and a heater part Hj which are adjacent to each other. 13. The semiconductor optical integrated circuit as set forth in claim 12 , wherein a same surface is formed by (i) an upper surface of each of the heater part H 0 and the heater part Hn and (ii) an upper surface of each of the slab parts of the optical waveguide. 14. The semiconductor optical integrated circuit as set forth in claim 7 , wherein the semiconductor layer is made of silicon. 15. The semiconductor optical integrated circuit as set forth in claim 7 , wherein the rib part is taller than the slab parts.

Assignees

Inventors

Classifications

  • Thermal instability, i.e. DC drift, of an optical modulator; Arrangements or methods for the reduction thereof · CPC title

  • semiconductor · CPC title

  • G02F1/0147Primary

    based on thermo-optic effects (G02F1/132 takes precedence) · CPC title

  • integrated waveguide · CPC title

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Frequently asked questions

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What does patent US10365507B2 cover?
Provided is a semiconductor optical integrated circuit which consumes less electric power than a conventional semiconductor optical integrated circuit. A semiconductor optical integrated circuit ( 1 ) includes a semiconductor layer ( 13 ) in which (i) an optical waveguide (LG) including heated section I 1 through I 3 and (ii) heater parts H 1 and H 2 are provided. The optical waveguide (LG)…
Who is the assignee on this patent?
Fujikura Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/0147. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 30 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).