Process for manufacturing a microelectronic device having a black surface, and microelectronic device

Patent metadata

Field	Value
Publication number	US-10364145-B2
Application number	US-201715460767-A
Country	US
Kind code	B2
Filing date	Mar 16, 2017
Priority date	Sep 26, 2016
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A roughened silicon surface is formed by a process including repetitively performed roughening cycles. Each roughening cycles including a step for depositing a non-planar polymeric layer over an area of a silicon body and a step for plasma etching the polymeric layer and the area of the silicon body etch in a non-unidirectional way. As a result, a surface portion of the silicon body is removed, in a non-uniform way, to a depth not greater than 10 nm.

First claim

The invention claimed is:

1. A process, comprising:
etching a trench into a silicon body, said trench including a sidewall surface and a bottom surface; and
roughening the sidewall surface and bottom surface of the trench to reduce surface reflectivity by performing a plurality of roughening cycles, wherein each roughening cycle includes:
depositing a polymeric layer having a non-planar surface profile over the sidewall surface and bottom surface of the trench; and
plasma etching the polymeric layer and the area of the silicon body at the sidewall surface and bottom surface of the trench in a non-unidirectional way to remove, in a non-uniform way, at least a portion of the polymeric layer and a surface portion of the area of the silicon body so as to replicate said non-planar surface profile of the polymeric layer on the sidewall surface and bottom surface of the trench.

2. The process according to claim 1 , wherein plasma etching comprises removing said surface portion to a depth that is not greater than 10 nm at the sidewall surface and bottom surface of the trench.

3. The process according to claim 1 , wherein depositing is carried out with a C 4 F 8 plasma and plasma etching is carried out with a C 4 F 8 and SF 6 plasma.

4. The process according claim 1 , wherein plasma etching comprises supplying a first flow of SF 6 and supplying a second flow of C 4 F 8 , wherein a ratio between the first flow and the second flow is approximately 1.5±20%.

5. The process according to claim 4 , wherein plasma etching comprises also supplying at least one of C and O 2 .

6. The process according to claim 4 , wherein depositing comprises supplying a third flow of C 4 F 8 , the third flow being greater than the second flow.

7. The process according to claim 6 , wherein a ratio between the third flow and the second flow is less than 1.5.

8. The process according to claim 6 , wherein the first flow is at a rate of 650 sccm, the second flow is at a rate of 400 sccm, and the third flow is at a rate of 425 sccm.

9. The process according to claim 1 , wherein depositing is carried out for a deposition time and plasma etching is carried out for an etching time, and wherein a ratio between the deposition time and the etching time during at least one roughening cycle is between approximately 0.25 and 0.4.

10. The process according to claim 9 , wherein said ratio is approximately 0.35.

11. The process according to claim 1 , wherein depositing is carried out for a deposition time and plasma etching is carried out for an etching time, and wherein a ratio between the deposition time and the etching time during a first roughening cycle is different from a ratio between the deposition time and the etching time during roughening cycles subsequent to said first roughening cycle.

12. The process according to claim 11 , wherein the etching time is substantially the same in all roughening cycles and wherein the deposition time is longer in the first roughening cycle than in roughening cycles subsequent to said first roughening cycle.

13. The process according to claim 12 , wherein the deposition time in the first roughening cycle is approximately 1.5 s and the deposition time in roughening cycles subsequent to said first roughening cycle is approximately 1.4 s.

14. The process according to claim 13 , wherein the etching time is approximately 4 s in all roughening cycles.

15. The process according to claim 1 , wherein depositing is carried out at a first plasma pressure, and plasma etching is carried out at a second plasma pressure, and wherein a ratio between the first and second pressures is approximately 1.8±5% in at least one roughening cycle.

16. The process according to claim 15 , wherein said ratio is the same in all roughening cycles except for a first roughening cycle.

17. The process according to claim 16 , wherein the first plasma pressure is approximately 80 mtorr in the first roughening cycle and the first plasma pressure is approximately 90 mtorr in roughening cycles subsequent to said first roughening cycle, and wherein the second plasma pressure is approximately 50 mtorr.

18. The process according to claim 1 , wherein the roughened sidewall surface and bottom surface of the trench, after performing said plurality of roughening cycles, has a reflectivity of less than 10%.

19. The process according to claim 1 , wherein said roughened sidewall surface and bottom surface of the trench is characterized by projections having a height-to-width ratio comprised between 1:1 and 1:5 and a high density.

Assignees

• St Microelectronics Srl

Inventors

• Somaschini Roberto
• Petruzza Pietro

Classifications

• G03B21/28

  Reflectors in projection beam {(in illumination beam G03B21/2066)} · CPC title

• G02B26/0833

  the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD (G02B26/0825 takes precedence; micromechanical devices in general B81B) · CPC title

• B81C1/00595 Primary

  Control etch selectivity · CPC title

• G03B21/008

  using micromirror devices · CPC title

• B81C1/00206 Primary

  Processes for functionalising a surface, e.g. provide the surface with specific mechanical, chemical or biological properties · CPC title