Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10361189-B2
Application number	US-201815955819-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Jun 9, 2017
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a trench electrode provided in a trench formed in the upper surface;
a trench insulating film provided between the trench electrode and the semiconductor substrate;
a MOS electrode provided over the semiconductor substrate near the trench electrode; and
a MOS insulating film provided between the MOS electrode and the semiconductor substrate,
wherein the semiconductor substrate comprises:
a first semiconductor layer of a first conductivity type that a lower end of the trench electrode has reached;
a second semiconductor layer of a second conductivity type that is provided over the first semiconductor layer and is in contact with the trench insulating film;
a third semiconductor layer of the first conductivity type provided over the second semiconductor layer;
a fourth semiconductor layer that is provided below the MOS electrode and is in contact with the MOS insulating film; and
one and the other of fifth semiconductor layers that are provided on both sides of the fourth semiconductor layer so as to sandwich the fourth semiconductor layer, and
wherein the semiconductor device further comprises a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.

2. The semiconductor device according to claim 1 ,
wherein the fourth semiconductor layer and the fifth semiconductor layers have the same conductivity type.

3. The semiconductor device according to claim 1 ,
wherein the MOS electrode, the MOS insulating film, the fourth semiconductor layer, and the fifth semiconductor layers form a depletion type MOS transistor.

4. The semiconductor device according to claim 1 ,
wherein the fifth semiconductor layers have the second conductivity type.

5. The semiconductor device according to claim 1 , further comprising a floating layer that is in contact with the other of the fifth semiconductor layers and is provided over the first semiconductor layer.

6. The semiconductor device according to claim 5 ,
wherein an impurity concentration of the fifth semiconductor layers is higher than an impurity concentration of the floating layer.

7. The semiconductor device according to claim 1 ,
wherein a plurality of the trench electrodes are provided,
wherein the second semiconductor layer and the third semiconductor layer are provided between the adjacent trench electrodes, and
wherein the MOS electrode is provided over the semiconductor substrate other than between the adjacent trench electrodes.

8. The semiconductor device according to claim 1 , further comprising a control unit that turns off conduction of a circuit from which a voltage is applied to the MOS electrode before turning off conduction of a circuit from which a voltage is applied to the trench electrode.

9. The semiconductor device according to claim 8 , comprising an IGBT gate pre-driver for a circuit from which a voltage is applied to the trench electrode and a MOS gate pre-driver for a circuit from which a voltage is applied to the MOS electrode,
wherein the control unit controls two systems of the IGBT gate pre-driver and the MOS gate pre-driver.

10. The semiconductor device according to claim 1 , comprising a control unit that turns off conduction of a circuit from which a voltage is applied to the MOS electrode at the same time when turning off conduction of a circuit from which a voltage is applied to the trench electrode.

11. The semiconductor device according to claim 10 , comprising a pre-driver common between a circuit from which a voltage is applied to the trench electrode and a circuit from which a voltage is applied to the MOS electrode,
wherein the control unit controls the pre-driver.

Assignees

• Renesas Electronics Corp

Inventors

• Kanda Ryo

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H01L29/7393

  Electricity · mapped topic

• H01L29/7397

  Electricity · mapped topic

• H01L21/02164

  Electricity · mapped topic

• H01L2924/13055

  Electricity · mapped topic