Memory device

Patent metadata

Field	Value
Publication number	US-10360976-B2
Application number	US-201815920531-A
Country	US
Kind code	B2
Filing date	Mar 14, 2018
Priority date	Mar 7, 2014
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node. The input value at the second input node of the sense amplifier is changed such that a change amount of the input value between two different temperatures T2 and (T2+ΔT) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than the change amount of the input value between two different temperatures T1 and (T1+ΔT) in the first temperature region of the memory cell, where ΔT is an increase amount of the temperature.

First claim

What is claimed is:

1. A memory device comprising:
a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;
a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node;
a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node; and
a reference current generation circuit provided with a replica circuit electrically connected to the second input node of the sense amplifier,
wherein:
the replica circuit includes a current mirror circuit having a first output terminal and a second output terminal and includes a first transistor and a second transistor,
the first output terminal of the current mirror circuit is electrically connected to the second input node, and
the second output terminal of the current mirror circuit is electrically connected to the first transistor and the second transistor, which are electrically connected in parallel via a third path different from the first and second paths.

2. The memory device according to claim 1 , wherein the replica circuit comprises a replica of the memory cell, the replica of the memory cell including the first transistor.

3. The memory device according to claim 1 , wherein the memory cell comprises a memory element and a cell transistor, and the replica circuit comprises a replica of the memory element and a replica of the cell transistor which is the first transistor.

4. The memory device according to claim 3 , wherein the replica of the memory element has a same structure as the memory element and the replica of the cell transistor has a same structure as the cell transistor.

5. The memory device according to claim 4 , wherein the memory element and the replica of the memory element include resistance change memory elements.

6. The memory device according to claim 4 , wherein the cell transistor and the replica of the cell transistor include MOSFETs.

7. The memory device according to claim 1 , wherein the first path comprises a column switch electrically connected to the memory cell, and the replica circuit comprises a replica of the column switch.

8. The memory device according to claim 7 , wherein the replica of the column switch has a same structure as the column switch.

9. The memory device according to claim 8 , wherein the column switch and the replica of the column switch include MOSFETs.

10. The memory device according to claim 1 , wherein the replica circuit further comprises a third transistor electrically connected to the reference current generation circuit and a fourth transistor electrically connected to the third transistor, and the third transistor and the fourth transistor provide the current mirror circuit.

11. The memory device according to claim 10 , wherein the replica circuit comprises a replica of the memory cell, and
wherein the fourth transistor and the replica of the memory cell are connected electrically in series between a power supply node and the ground node.

12. The memory device according to claim 10 , wherein the first path comprises a column switch electrically connected to the memory cell, and the replica circuit comprises a replica of the column switch, and
wherein the fourth transistor and the replica of the column switch are connected electrically in series between a power supply node and the ground node.

13. A memory device comprising:
a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;
a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node;
a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node;
a reference current generation circuit including a first node and a second node, the first node being electrically connected to the second input node of the sense amplifier; and
a replica circuit electrically connected to the second node of the reference current generation circuit, the replica circuit including a current mirror circuit having a first output terminal and a second output terminal, and the replica circuit including a first transistor and a second transistor,
wherein:
the first output terminal of the current mirror circuit is electrically connected to the second node of the reference current generation circuit, and
the second output terminal of the current mirror circuit is electrically connected to the first transistor and the second transistor, which are electrically connected in parallel.

14. The memory device according to claim 13 , further comprising another current mirror circuit including a third transistor and a fourth transistor,
wherein:
the second path includes the third transistor, and
the reference current generation circuit includes the fourth transistor.

15. The memory device according to claim 14 , wherein:
a gate of the third transistor is electrically connected to the first node of the reference current generation circuit,
a drain of the third transistor is electrically connected to the second input node,
a gate and a drain of the fourth transistor are electrically connected to the first and second nodes of the reference current generation circuit, and
a source of the fourth transistor is electrically connected to a ground node.

16. The memory device according to claim 13 , wherein a current flowing in the second path varies based on a first current obtained by adding a second current flowing in the first output terminal of the current mirror circuit to a third current flowing in the second node of the reference current generation circuit.

17. A memory device comprising:
a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;
a memory cell array including memory cells;
a first path including one of the memory cells to be selectively connected to the first input node and provided between the first input node and a ground node;
a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node; and
a reference current generation circuit provided with a replica circuit other than the memory cells, the reference current generation circuit being electrically connected to the second input node of the sense amplifier,
wherein:
the replica circuit includes a current mirror circuit having a first output terminal and a second output terminal and includes a first transistor and a second transistor,
the first output terminal of the current mirror circuit is electrically connected to the second input node, and
the second output terminal of the current mirror circuit is electrically connected to the first transistor and the second transistor, which are electrically connected in parallel.

Assignees

• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title