Memory system and data transmission method

Patent metadata

Field	Value
Publication number	US-10360953-B2
Application number	US-201815937518-A
Country	US
Kind code	B2
Filing date	Mar 27, 2018
Priority date	Aug 3, 2002
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

First claim

What is claimed is:

1. A memory system comprising:
a memory controller having a clock output, a command/address output, a first data output, a first data timing output, a second data output, and a second data timing output;
a first memory device having a first clock input, a first command/address input, a first data input, and a first data timing input;
a second memory device having a second clock input, a second command/address input, a second data input, and a second data timing input;
a first wiring coupled between the clock output and the first clock input;
a second wiring coupled between the first clock input and the second clock input;
a third wiring coupled between the command/address output and the first command/address input;
a fourth wiring coupled between the first command/address input and the second command/address input;
a fifth wiring coupled between the first data output and the first data input;
a sixth wiring coupled between the first data timing output and the first data timing input;
a seventh wiring coupled between the second data output and the second data input; and
an eighth wiring coupled between the second data timing output and the second data timing input;
wherein the command/address output is synchronized to the clock output, the first data output is synchronized to the first data timing output and the second data output is synchronized to the second data timing output;
wherein the memory controller delays the second data output and the second data timing output with respect to the first data output and the first data timing output.

2. The memory system of claim 1 , wherein the memory controller comprises a third data input coupled to the first data output, a third data timing input coupled to the first data timing output, a fourth data input coupled to the second data output, and a fourth data timing input coupled to the second data timing output, and the first memory device comprises a third data output coupled to the first data input and a third data timing output coupled to the first data timing input, and the second memory device comprises a fourth data output coupled to the second data input and a fourth data timing output coupled to the second data timing input.

3. The memory system of claim 1 , wherein an edge of the clock output is aligned between edges of the command/address output.

4. The memory system of claim 1 , wherein an edge of the first data timing output is aligned between edges of the first data output and an edge of the second data timing output is aligned between edges of the second data output.

5. The memory system of claim 1 , wherein an edge of the first data timing output is aligned with an edge of the first data output and an edge of the second data timing output is aligned with an edge of the second data output.

6. The memory system of claim 1 , wherein the first data output and the second data output are double data rate (DDR) outputs.

7. The memory system of claim 1 , wherein the first data timing output and the second data timing output are data strobe (DQS) outputs.

8. The memory system of claim 1 , wherein the first data timing output and the second data timing output have the same frequency as the clock output.

9. The memory system of claim 1 , wherein the first data timing output and the second data timing output are data phase (DPS) outputs.

10. The memory system of claim 1 , wherein the first data timing output and the second data timing output have a pulse frequency lower than the frequency of the clock output.

11. The memory system of claim 10 , wherein the first data timing output and the second data timing output have a pulse frequency equal to 25% of the frequency of the clock output.

12. The memory system of claim 1 , wherein the first wiring has substantially the same length as the third wiring and the second wiring has substantially the same length as the fourth wiring.

13. The memory system of claim 1 , wherein the fifth wiring has substantially the same length as the sixth wiring and the seventh wiring has substantially the same length as the eighth wiring.

14. The memory system of claim 13 , wherein the first wiring has substantially the same length as the third wiring and the second wiring has substantially the same length as the fourth wiring.

15. The memory system of claim 1 , wherein the first memory device and the second memory device are mounted on a memory module.

16. The memory system of claim 15 , wherein the memory controller is mounted on a motherboard having a module connector to which the memory module is connected.

17. The memory system of claim 1 , further comprising:
a third memory device having a third clock input coupled to the first wiring, a third command/address input coupled to the third wiring, a third data input coupled to a ninth wiring, and a third data timing input coupled to a tenth wiring; and
a fourth memory device having a fourth clock input coupled to the second wiring, a fourth command/address input coupled to the fourth wiring, a fourth data input coupled to an eleventh wiring, and a fourth data timing input coupled to a twelfth wiring;
wherein the memory controller comprises a third data output coupled to the ninth wiring, a third data timing output coupled to the tenth wiring, a fourth data output coupled to the eleventh wiring, and a fourth data timing output coupled to the twelfth wiring;
wherein the third data output is synchronized to the third data timing output and the fourth data output is synchronized to the fourth data timing output;
wherein the memory controller delays the fourth data output and the fourth data timing output with respect to the third data output and the third data timing output.

18. The memory system of claim 17 , wherein the delay between the fourth data output and the third data output is the same as the delay between the second data output and the first data output.

19. The memory system of claim 18 , wherein there is no delay between the first data output and the third data output.

20. A memory system comprising:
a memory controller having a clock output, a command/address output, a first data output, a first data timing output, a second data output, and a second data timing output;
a first memory device having a first clock input, a first command/address input, a first data input, and a first data timing input;
a second memory device having a second clock input, a second command/address input, a second data input, and a second data timing input;
wherein the clock output is coupled to the first clock input and the second clock input, the command/address output is coupled to the first command/address input and the second command/address input, the first data output is coupled to the first data input, the first data timing output is coupled to the first data timing input, the second data output is coupled to the second data input, and the second data timing output is coupled to the second data timing input;
wherein the command/address output is synchronized to the clock output, the first data output is synchronized to the first data timing output and the second data output is synchronized to the second data timing output;
wherein the first memory device receives the clock output and the command/address output with a first delay, and the second memory device receives the clock output and the command/address output with a second delay greater than the first delay;
wherein the memory controller delays the second data output and the second data timing output

Assignees

• Ps4 Luxco Sarl
• Longitude Licensing Ltd

Inventors

• Matsui Yoshinori

Classifications

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F13/4243 Primary

  with synchronous protocol · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title