Memory system and method for wear-leveling by swapping memory cell groups

Patent metadata

Field	Value
Publication number	US-10360157-B2
Application number	US-201715597866-A
Country	US
Kind code	B2
Filing date	May 17, 2017
Priority date	Jun 30, 2016
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

First claim

What is claimed is:

1. A memory system, comprising:
a memory device including a memory block, the memory block including a plurality of memory cell groups;
an address translator that maps a logical address of a data to a physical address of the memory block; and
a controller configured to:
divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and
control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses,
wherein when a hot data is detected, the controller controls the address translator to map a logical address of the hot data to a physical address of the second memory cell group, and when the predetermined period of time elapses, the controller controls the address translator to remap the logical address of the hot data to the physical address of the selected first cell group.

2. The memory system of claim 1 , wherein the selected first memory cell group is disposed adjacent to the at least second memory cell group in a first direction.

3. The memory system of claim 1 , wherein switching the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups includes re-mapping a logical address that is mapped to a physical address of the selected first memory cell group to the physical address of the at least one second memory cell group.

4. The memory system of claim 3 , wherein the controller is further configured to detect the hot data.

5. The memory system of claim 4 , wherein whenever a new hot data is detected, the controller controls the address translator to re-map a logical address of an existing hot data that is mapped to the physical address of the at least one second memory cell group to a physical address of a corresponding original memory cell group for the logical address of the existing hot data, and map a logical address of the new hot data to the physical address of the at least one second memory cell group.

6. The memory system of claim 4 , wherein the controller detects a data that is accessed by a host a number of times equal to or greater than a reference number and classifies the data as the hot data.

7. The memory system of claim 6 , wherein the controller detects the hot data by counting the number of times that a read operation or a write operation is performed for a data and comparing the counted number of times with the reference number.

8. The memory system of claim 1 , wherein each of the plurality of the memory cell groups includes a plurality of memory cells coupled to one word line.

9. A method for operating a memory system including a memory device including a memory block, the memory block including a plurality of memory cell groups, comprising:
dividing the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group;
mapping a logical address of a data to a physical address of the first memory cell groups of the memory block
mapping a logical address of a hot data to a physical address of the at least one second memory cell group when the hot data is detected; and
shifting the at least one second memory cell group among the plurality of the first memory cell groups by switching the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses, wherein the logical address of the hot data is re-mapping to the physical address of the selected first memory cell group when the predetermined period of time elapses.

10. The method of claim 9 , wherein switching the at least one second memory cell group with a selected first memory cell group includes:
re-mapping a logical address that is mapped to a physical address of the selected first memory cell group to the physical address of the at least one second memory cell group.

11. The method of claim 9 , wherein the selected first memory cell group is disposed adjacent to the first memory cell group in a first direction among the first memory cell groups.

12. The method of claim 9 , wherein the selected first memory cell group is defined as the new at least one second memory cell group and the previous at least one second memory cell group is defined as one of the first memory cell groups.

13. The method of claim 10 , further comprising:
detecting the hot data.

14. The method of claim 13 , wherein the mapping of the logical address of the hot data to the physical address of the second memory cell group includes:
whenever a new hot data is detected, re-mapping a logical address of an existing hot data that is mapped to the physical address of the second memory cell group to a physical address of a corresponding original first memory cell group.

15. The method of claim 13 , wherein detecting the hot data includes detecting a data that is accessed by a host a number of times equal to or greater than a reference number.

16. The method of claim 15 , wherein the detecting of the hot data includes:
counting the number of times that a read operation or a write operation is requested by the host to be performed for a data; and
comparing the counted number of times with the reference number.

17. The method of claim 9 , wherein each of the plurality of the memory cell groups includes a plurality of memory cells coupled to one word line.

Assignees

• Sk Hynix Inc

Inventors

• Kim Dong-Gun
• Kim Yong-Ju
• JO Sang-Gu
• Hong Do-Sun

Classifications

• G06F2212/7211

  Wear leveling · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F2212/1016

  Performance improvement · CPC title