Circuit arrangement for clock synchronization

Patent metadata

Field	Value
Publication number	US-10356736-B2
Application number	US-201715600862-A
Country	US
Kind code	B2
Filing date	May 22, 2017
Priority date	Jun 21, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.

First claim

What is claimed is:

1. A circuit arrangement, comprising:
an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency, wherein the sampling frequency is smaller than the ADC frequency; wherein the decimation circuit comprises a numerically controlled oscillator for providing the first signal having the sampling frequency; a timer circuit providing a second signal having a timer frequency and an integer decimation enable signal to control the timing of the decimation circuit; and
a feedback control circuit configured to determine a phase difference between the second signal and the first signal;
wherein the decimation circuit comprises a first decimation circuit arranged in a first clock domain and a second decimation circuit arranged in a second clock domain; and
wherein the first decimation circuit or the second decimation circuit comprises a fractional decimation circuit configured to provide the first signal having the sampling frequency.

2. The circuit arrangement of claim 1 , further comprising:
a feedback control circuit configured to adjust the phase difference between the second signal and the first signal to a predefined value.

3. The circuit arrangement of claim 2 ,
wherein the feedback control circuit is configured to adjust at least one of the timer circuit or the decimation circuit to provide the phase difference of the second signal and the first signal with the predefined value.

4. The circuit arrangement of any one of claims 2 ,
wherein the feedback control circuit comprises a sensor configured to measure a current phase difference between the second signal and the first signal.

5. The circuit arrangement of claim 1 ,
wherein the timer circuit comprises a timer numerically controlled oscillator providing the second signal having the timer frequency.

6. The circuit arrangement of claim 1 ,
wherein the decimation circuit comprises a decimation numerically controlled oscillator providing the first signal having the sampling frequency.

7. The circuit arrangement of claim 1 , further comprising:
a baseband circuit configured to demodulate the first signal provided by the decimation circuit.

8. The circuit arrangement of claim 7 ,
wherein the baseband circuit is configured to receive a signal having a fixed predefined frequency.

9. A circuit arrangement adapted for clock synchronization and signal conversion used in a mobile radio communication device, the circuit arrangement comprising:
an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency, wherein the sampling frequency is smaller than the ADC frequency; wherein the decimation circuit comprises a numerically controlled oscillator for providing the first signal having the sampling frequency;
a timer circuit providing a second signal having a timer frequency and an integer decimation enable signal to control the timing of the decimation circuit;
a feedback control circuit configured to determine a frequency difference between the timer frequency and the sampling frequency;
a feedback control circuit configured to adjust at least one of the timer frequency or the sampling frequency so that the timer frequency and the sampling frequency are aligned;
wherein the feedback control circuit is configured to adjust at least one of the timer circuit or the decimation circuit to provide the frequency difference of the second signal and the first signal with a predefined value; and
wherein the feedback control circuit comprises a sensor configured to measure a current phase difference between the second signal and the first signal.

10. The circuit arrangement of claim 9 ,
wherein the timer circuit comprises a timer numerically controlled oscillator providing the second signal having the timer frequency.

11. The circuit arrangement of claim 9 ,
wherein the decimation circuit comprises a decimation numerically controlled oscillator providing the first signal having the sampling frequency.

12. The circuit arrangement of claim 9 ,
wherein the decimation circuit comprises a fractional decimation circuit configured to provide the first signal having the sampling frequency.

13. The circuit arrangement of claim 9 , further comprising:
a baseband circuit configured to demodulate the first signal provided by the decimation circuit.

14. The circuit arrangement of claim 13 ,
wherein the baseband circuit is configured to receive a signal having a fixed predefined frequency.

15. A mobile radio communication device, comprising:
a radio frequency circuit; and
a circuit arrangement, comprising:
an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency,
wherein the sampling frequency is smaller than the ADC frequency;
wherein the decimation circuit comprises a numerically controlled oscillator for providing the first signal having the sampling frequency;
wherein the decimation circuit comprises a first decimation circuit arranged in a first clock domain and a second decimation circuit arranged in a second clock domain; a timer circuit providing a second signal having a timer frequency and an integer decimation enable signal to control the timing of the decimation circuit; and
a feedback control configured to determine a phase difference between the second signal and the first signal;
wherein the first decimation circuit or the second decimation circuit comprises a fractional decimation circuit configured to provide the first signal having the sampling frequency.

16. The mobile radio communication device of claim 15 , configured as a mobile radio communication terminal device.

Assignees

• Intel Ip Corp

Inventors

• Reinhardt Steffen
• Bode Peter

Classifications

• H04W56/005

  compensating for timing error by adjustment in the receiver · CPC title

• H04W4/10

  Push-to-Talk [PTT] or Push-On-Call services · CPC title

• H04W56/001 Primary

  Synchronization between nodes · CPC title

• H04W24/02

  Arrangements for optimising operational condition · CPC title

• H04W56/0035

  detecting errors in frequency or phase · CPC title