Heterogeneous channel capacities in an interconnect

Patent metadata

Field	Value
Publication number	US-10355996-B2
Application number	US-201414519639-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Oct 9, 2012
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

First claim

What is claimed is:

1. A method, comprising:
determining a width for each of a plurality of virtual channels in a network on chip (NoC) comprising a plurality of hosts interconnected by a plurality of physical wires to form the plurality of virtual channels, based on at least one NoC performance objective for the each of the plurality of virtual channels or a maximum data flow of the each of the plurality of virtual channels, such that at least one of the plurality of virtual channels has a different width than at least another one of the plurality of virtual channels, the at least one NoC performance objective comprising at least one of a bandwidth requirement and a latency requirement; and
providing a message reformatter between connected ones of the plurality of virtual channels, wherein the provided message reformatter is configured to adjust flits of one or more messages between the connected ones of the plurality of virtual channels.

2. The method of claim 1 , wherein the provided message reformatter is configured to adjust the one or more messages such that all source and destination end host pairs of the NoC maintain end-to-end message size and message format consistency.

3. The method of claim 1 , wherein the maximum data flow of the each of the plurality of virtual channels is determined from an application of a maximum flow algorithm on a graph of data traffic of the plurality of virtual channels.

4. The method of claim 1 , wherein the determining the width of each of the plurality of virtual channels further comprises applying linear programming to determine the width that meets the at least one NoC performance objective while minimizing at least one specified cost function.

5. The method of claim 4 , wherein the applying linear programing further comprises constructing a list of constraints for meeting virtual and physical channel performance requirements, and wherein at least one objective function is derived for each of the at least one NoC performance objective based on the list of constraints.

6. The method of claim 1 , wherein shortest path routing is applied to the plurality of virtual channels to meet the latency requirement.

7. A non-transitory computer readable medium storing instructions for executing a process, comprising:
determining a width for each of a plurality of virtual channels in a network on chip (NoC) comprising a plurality of hosts interconnected by a plurality of physical wires to form the plurality of virtual channels, based on a maximum data flow of the each of the plurality of virtual channels, such that at least one of the plurality of virtual channels has a different width than at least another one of the plurality of virtual channels,
wherein the instructions further comprise providing a message reformatter between connected ones of the plurality of virtual channels, wherein the provided message reformatter is configured to adjust flits of one or more messages between the connected ones of the plurality of virtual channels;
wherein the maximum data flow of the each of the plurality of virtual channels is determined from an application of a maximum flow algorithm on a graph of data traffic of the plurality of virtual channels.

8. The non-transitory computer readable medium of claim 7 , wherein the provided message reformatter is configured to adjust the one or more messages such that all source and destination end host pairs of the NoC maintain end-to-end message size and message format consistency.

9. The non-transitory computer readable medium of claim 7 , wherein the maximum data flow is indicative of a maximum bandwidth required for the plurality of virtual channels.

10. The non-transitory computer readable medium of claim 7 , wherein the determining the width of each of the plurality of virtual channels further comprises applying linear programming to determine the width that meets at least one NoC performance objective while minimizing at least one specified cost function.

11. The non-transitory computer readable medium of claim 10 , wherein the applying linear programing further comprises constructing a list of constraints for meeting virtual and physical channel performance requirements, and wherein the instructions further comprise deriving at least one objective function for each of the at least one NoC performance objective based on the list of constraints.

12. The non-transitory computer readable medium of claim 10 , wherein the at least one NoC performance objective comprises a latency requirement, and wherein the instructions further comprise applying shortest path routing to the plurality of virtual channels to meet the latency requirement.

13. A system, comprising:
a width adjustment module configured to determine a width for each of a plurality of virtual channels in a network on chip (NoC) comprising a plurality of hosts interconnected by a plurality of physical wires to form the plurality of virtual channels, based on at least one NoC performance objective for the each of the plurality of virtual channels or a maximum data flow of the each of the plurality of virtual channels, such that at least one of the plurality of virtual channels has a different width than at least another one of the plurality of virtual channels, the at least one NoC performance objective comprising at least one of a bandwidth requirement and a latency requirement; and
a message reformatter module configured to provide a message reformatter between connected ones of the plurality of virtual channels, wherein the provided message reformatter adjusts flits of one or more messages between the connected ones of the plurality of virtual channels.

14. The system of claim 13 , wherein the provided message reformatter is configured to adjust one or more messages such that all source and destination end host pairs of the NoC maintain end-to-end message size and message format consistency.

15. The system of claim 13 , wherein the maximum flow of the each of the plurality of virtual channels is determined by the width adjustment module from an application of a maximum flow algorithm on a graph of data traffic of the plurality of virtual channels.

16. The system of claim 13 , wherein the width adjustment module is configured to determine the width of each of the plurality of virtual channels by applying linear programming to determine the width that meets the at least one NoC performance objective while minimizing at least one specified cost function.

17. The system of claim 16 , wherein the width adjustment module is configured to apply linear programing by constructing a list of constraints for meeting virtual and physical channel performance requirements and further configured to derive at least one objective function for each of the at least one NoC performance objective based on the list of constraints.

Assignees

• Netspeed Systems

Inventors

• Kumar Sailesh
• Philip Joji
• Norige Eric
• Mitra Sundari

Classifications

• H04L47/122 Primary

  by diverting traffic away from congested entities · CPC title

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L43/062

  related to network traffic · CPC title