Comb terminals for planar integrated circuit inductor

Patent metadata

Field	Value
Publication number	US-10355642-B2
Application number	US-201514722607-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	May 27, 2015
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.

First claim

What is claimed is:

1. An apparatus comprising:
a conductive loop formed from a first conductive layer, the conductive loop comprising a first terminal and a second terminal,
the first terminal comprising at least one first conductive finger in the first conductive layer,
the second terminal comprising at least one second conductive finger in the first conductive layer, the at least one second conductive finger being interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger;
at least one first conductive via coupled to a second conductive layer and coupled to the at least one first conductive finger, respectively;
at least one second conductive via coupled to the second conductive layer and coupled to the at least one second conductive finger, respectively;
a first conductive structure formed in the second conductive layer and coupled to the at least one first conductive via; and
a second conductive structure formed in the second conductive layer and coupled to the at least one second conductive via,
wherein the first conductive structure and the second conductive structure are parallel conductive lines extending approximately radially with respect to a center of the conductive loop.

2. The apparatus as recited in claim 1 , wherein the first conductive layer is thicker than the second conductive layer.

3. The apparatus as recited in claim 1 , wherein the first conductive layer has a lower resistivity than the second conductive layer.

4. The apparatus as recited in claim 1 , wherein the parallel conductive lines form a capacitor coupled in parallel with the conductive loop.

5. The apparatus as recited in claim 1 , wherein the first conductive layer has a first thickness at least twice a second thickness of the second conductive layer.

6. The apparatus as recited in claim 1 , further comprising:
a serpentine gap in the first conductive layer, the serpentine gap being disposed between the first terminal and the second terminal and having a constant width.

7. The apparatus as recited in claim 1 , wherein the at least one first conductive finger is parallel to the at least one second conductive finger and the at least one first conductive finger and the at least one second conductive finger each extend in a direction tangential to the conductive loop.

8. The apparatus as recited in claim 1 , wherein the conductive loop forms at least a portion of an inductor.

9. The apparatus as recited in claim 1 , further comprising:
an additional conductive loop formed from the first conductive layer, the additional conductive loop comprising a portion of the conductive loop or the first and second terminals.

10. A method of manufacturing an integrated circuit comprising:
forming a conductive loop from a first conductive layer, the conductive loop comprising a first terminal and a second terminal, the first terminal comprising at least one first conductive finger in the first conductive layer, and the second terminal comprising at least one second conductive finger in the first conductive layer, the at least one second conductive finger being interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger;
forming at least one first conductive via coupled to a second conductive layer and coupled to the at least one first conductive finger, respectively;
forming at least one second conductive via coupled to the second conductive layer and coupled to the at least one second conductive finger, respectively; and
forming a first conductive structure in the second conductive layer and coupled to the at least one second conductive via; and
forming a second conductive structure in the second conductive layer and coupled to the at least one second conductive via,
wherein the first conductive structure and the second conductive structure are parallel conductive lines extending approximately radially with respect to a center of the conductive loop.

11. The method as recited in claim 10 , wherein forming the conductive loop forms a serpentine gap having a constant width in the first conductive layer and being disposed between the first terminal and the second terminal.

12. The method as recited in claim 10 , further comprising:
forming the second conductive layer, the second conductive layer being disposed between a substrate and the first conductive layer.

13. The method as recited in claim 10 , wherein the first conductive layer has a resistivity less than the resistivity of the second conductive layer.

14. An integrated circuit formed by the method recited in claim 10 .

15. The apparatus, as recited in claim 1 , further comprising:
an additional conductive structure formed in the second conductive layer and coupled to the at least one first conductive finger by an additional conductive via, the additional conductive structure and the first conductive structure being disposed in positions alternating with the second conductive structure.

16. The method, as recited in claim 10 , further comprising:
forming an additional conductive structure in the second conductive layer and coupled to the at least one first conductive finger by an additional conductive via, the additional conductive structure and the first conductive structure being disposed in positions alternating with the second conductive structure.

17. The apparatus, as recited in claim 1 , wherein the conductive loop is included in a multi-loop inductor and the first terminal and the second terminal adjoin the conductive loop and a second conductive loop of the multi-loop inductor.

18. The apparatus, as recited in claim 1 , wherein the conductive loop is included in a dual-loop inductor and the first terminal and the second terminal are disposed at a first end of the dual-loop inductor.

19. The method, as recited in claim 10 , wherein the conductive loop is included in a multi-loop inductor and the first terminal and the second terminal adjoin the conductive loop and a second conductive loop of the multi-loop inductor.

20. The method, as recited in claim 10 , wherein the conductive loop is included in a dual-loop inductor and the first terminal and the second terminal are disposed at a first end of the dual-loop inductor.

Assignees

• Silicon Lab Inc

Inventors

• Caffee Aaron J

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H03B2200/0016

  including a ring, disk or loop shaped resonator · CPC title

• H01F2017/0086

  on semiconductor substrate · CPC title

• H03B5/00 Primary

  Generation of oscillations using amplifier with regenerative feedback from output to input (H03B9/00, H03B15/00 take precedence) · CPC title