Semiconductor module

Patent metadata

Field	Value
Publication number	US-10355619-B2
Application number	US-201716076444-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Mar 15, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device.

First claim

The invention claimed is:

1. A semiconductor module including a power conversion circuit, comprising:
an insulating substrate;
a first transistor constituting an upper arm of the power conversion circuit;
a second transistor constituting a lower arm of the power conversion circuit and electrically series-coupled to the first transistor;
a first input interconnection pattern disposed on the insulating substrate and coupled to a positive-side input terminal for supplying positive power to the power conversion circuit;
a second input interconnection pattern disposed on the insulating substrate and coupled to a negative-side input terminal for supplying negative power to the power conversion circuit;
an output interconnection pattern disposed on the insulating substrate and coupled to an output terminal for outputting output power of the power conversion circuit; and
an absorbing device configured to absorb surge voltage in the power conversion circuit,
wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted,
wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted,
wherein the second input interconnection pattern includes an absorbing-device connecting area that is disposed between the first-transistor mounting area and the second-transistor mounting area,
wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device,
wherein the second input interconnection pattern includes a capacitor connecting area seamlessly connected to an end of the absorbing-device connecting area,
wherein the absorbing-device connecting area and the capacitor connecting area are disposed on the insulating substrate such as to surround the first-transistor mounting area, and
wherein the capacitor connecting area is electrically coupled to the first-transistor mounting area through a capacitor.

2. The semiconductor module as claimed in claim 1 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first-transistor mounting area, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the second-transistor mounting area, and are electrically coupled in parallel.

3. The semiconductor module as claimed in claim 1 , comprising a plurality of said absorbing devices, wherein the plurality of absorbing devices are disposed at spaced intervals.

4. A semiconductor module including a power conversion circuit, comprising:
an insulating substrate;
a first transistor constituting an upper arm of the power conversion circuit;
a second transistor constituting a lower arm of the power conversion circuit and electrically series-coupled to the first transistor;
a first input interconnection pattern disposed on the insulating substrate and coupled to a positive-side input terminal for supplying positive power to the power conversion circuit;
a second input interconnection pattern disposed on the insulating substrate and coupled to a negative-side input terminal for supplying negative power to the power conversion circuit;
an output interconnection pattern disposed on the insulating substrate and coupled to an output terminal for outputting output power of the power conversion circuit; and
an absorbing device configured to absorb surge voltage in the power conversion circuit,
wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted,
wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted,
wherein the second input interconnection pattern includes an absorbing-device connecting area that is disposed between the first-transistor mounting area and the second-transistor mounting area, and
wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device,
the semiconductor module further comprising an auxiliary interconnection pattern disposed on the insulating substrate between the absorbing-device connecting area and the first-transistor mounting area,
wherein the absorbing device includes a first circuit element and a second circuit element,
wherein the first circuit element electrically couple the auxiliary interconnection pattern and the first-transistor mounting area, and
wherein the second circuit element electrically couple the auxiliary interconnection pattern and the absorbing-device connecting area.

5. The semiconductor module as claimed in claim 4 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first-transistor mounting area, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the second-transistor mounting area, and are electrically coupled in parallel.

6. The semiconductor module as claimed in claim 4 , comprising a plurality of said absorbing devices, wherein the plurality of absorbing devices are disposed at spaced intervals.

Assignees

• Sumitomo Electric Industries

Inventors

• Oomori Hirotaka

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W90/00

  Package configurations · CPC title