Dual phased array with single polarity beam steering integrated circuits

Patent metadata

Field	Value
Publication number	US-10355370-B2
Application number	US-201715669575-A
Country	US
Kind code	B2
Filing date	Aug 4, 2017
Priority date	Aug 4, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

First claim

What is claimed is:

1. A phased array comprising:
a laminar substrate;
a plurality of elements on the laminar substrate forming a patch phased array;
a first set of integrated circuits on the laminar substrate, the first set of integrated circuits being single polarity integrated circuits,
the first set of integrated circuits connected with a first set of the plurality of elements, the first set of integrate circuits configured to operate using first signals having a first polarity; and
a second set of integrated circuits on the laminar substrate, the second set of integrated circuits being single polarity integrated circuits,
the second set of integrated circuits connected with a second set of the plurality of elements, the second set of integrated circuits configured to operate using second signals having a second polarity,
the first polarity being substantially orthogonal to the second polarity.

2. The phased array as defined by claim 1 wherein the first set of elements and the second set of elements share at least one of the plurality of elements (“shared element”).

3. The phased array as defined by claim 2 wherein the first set of elements includes at least one element that is not connected to any of the integrated circuits in the second set of integrated circuits.

4. The phased array as defined by claim 2 wherein the shared element is configured to operate using two orthogonal signals substantially simultaneously.

5. The phased array as defined by claim 1 further comprising:
first RF lines connecting the first set of integrated circuits to the elements in the first sets of elements; and
second RF lines connecting the second set of integrated circuits to the elements in the second sets of elements.

6. The phased array as defined by claim 5 wherein a given first RF line contacts a given element in the first set of elements at a first point, a given second RF line contacts the given element in the first set of elements at a second point, the first and second points being spaced physically about 90 degrees apart,
the given element being shared between the first and second sets of integrated circuits.

7. The phased array as defined by claim 6 wherein a given element in the first set of elements is spaced apart between about 0.4 and 0.6 times the given frequency from an adjacent element in the first set of elements.

8. The phased array as defined by claim 6 wherein the given element is configured to be excited in a horizontal polarity and/or a vertical polarity at the same time.

9. The phased array as defined by claim 1 wherein the first set of integrated circuits and second set of integrated circuits are substantially the same type of integrated circuit.

10. The phased array as defined by claim 1 wherein each integrated circuit has more than one interface, each of the more than one interface being connected with one of the plurality of elements, the interfaces on a single integrated circuit being connected to different elements.

11. The phased array as defined by claim 1 wherein the first set of elements has no more than a first number of elements, further wherein the second set of elements has no more than a second number of elements, the first number being equal to the second number.

12. The phased array as defined by claim 1 wherein the plurality of elements includes a given element that is not part of the first set of elements and not part of the second set of elements.

13. The phased array as defined by claim 1 wherein the plurality of elements includes a first element, a second element, a third element and a fourth element, the first, second, third and fourth elements forming a line, the second element being between the first and third elements, the third element being between the second and fourth elements,
the first element having a first connection point pattern,
the second element having a second connection point pattern,
the third element having a third connection point pattern,
the fourth element having a fourth connection point pattern,
the first and third connection point patterns being the same,
the second and fourth connection point patterns being the same,
the first connection point pattern being different from the second point connection pattern to form alternating connection point patterns from the first to the fourth elements.

14. A phased array comprising:
a laminar substrate;
a plurality of elements on the laminar substrate forming a patch phased array;
a first set of integrated circuits on the laminar substrate, the first set of integrated circuits connected with a first set of the plurality of elements, each element of the first set of elements having connection points forming a first pattern on each of the first set of elements; and
a second set of integrated circuits on the laminar substrate, the second set of integrated circuits connected with a second set of the plurality of elements, each element of the second set of elements having connection points forming a second pattern on each of the second set of elements,
the first and second sets of integrated circuits being single polarity integrated circuits,
the first and second patterns configured so that the first set of elements operate at a first polarity and the second set of elements operate at a second polarity orthogonal to the first polarity.

15. The phased array as defined by claim 14 wherein the first set of elements and the second set of elements share at least one of the plurality of elements (“shared element”).

16. The phased array as defined by claim 14 wherein the first set of elements includes at least one element that is not connected to any of the integrated circuits in the second set of integrated circuits.

17. The phased array as defined by claim 14 wherein the shared element is configured to operate using two orthogonal signals substantially simultaneously.

18. The phased array as defined by claim 14 further comprising:
first RF lines connecting the first set of integrated circuits to the elements in the first sets of elements according to the first pattern; and
second RF lines connecting the second set of integrated circuits to the elements in the second sets of elements according to the second pattern.

19. The phased array as defined by claim 14 wherein the first set of integrated circuits and second set of integrated circuits are substantially the same type of integrated circuit.

20. The phased array as defined by claim 14 wherein the plurality of elements includes a first element, a second element, a third element and a fourth element, the first, second, third and fourth elements forming a line, the second element being between the first and third elements, the third element being between the second and fourth elements,
the first element having the first pattern,
the second element having the second pattern,
the third element having the first pattern,
the fourth element having the second pattern.

21. A method of forming a patch phased array, the method comprising:
forming a plurality of elements on a laminar substrate;
securing a first set of single polarity integrated circuits on the laminar substrate;
connecting the first set of integrated circuits with a first set of the plurality of elements so that the first set of elements is configured to operate using first signals having a first polarity;
securing a second set of single polarity integrated circuits on the laminar substrate;
connecting the second set of integrated circuits wit

Assignees

• Anokiwave Inc

Inventors

• Mcmorrow Robert J
• Gresham Robert Ian

Classifications

• H01Q3/34 Primary

  by electrical means (active lenses or reflecting arrays H01Q3/46) · CPC title

• H01Q21/065

  Patch antenna array · CPC title

• H01Q21/22 Primary

  Antenna units of the array energised non-uniformly in amplitude or phase, e.g. tapered array or binomial array · CPC title

• H01Q1/2283

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q1/42

  Housings not intimately mechanically associated with radiating elements, e.g. radome · CPC title