Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cells

Patent metadata

Field	Value
Publication number	US-10355207-B2
Application number	US-201815927635-A
Country	US
Kind code	B2
Filing date	Mar 21, 2018
Priority date	Mar 23, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

First claim

The invention claimed is:

1. A method for forming a non-volatile memory cell for switching said memory cell from an unformed state to a formed state, said memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode, the method comprising
performing a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make said layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active, several laser shots being able to be emitted successively towards the layer of insulating material with, each, a laser shot power flux density greater than the laser shot power flux density of the preceding laser shot.

2. The forming method according to claim 1 , further comprising:
a) reading the memory cell,
b) detecting the formed or unformed state of said memory cell,
c) when the memory cell is in an unformed state, implementing laser shots,
d) when the memory cell is in a formed state, carrying out a post-forming cycle to place said cell in an operating state.

3. The forming method according to claim 2 , wherein steps a)-c) are repeated as long as the memory cell is in an unformed state, the power flux density of the laser shot being increased at each repetition of step c).

4. The forming method according to claim 2 , wherein the post-forming cycle of step d) comprises several cycles, successive and reversible, of switching between the high resistance state and the low resistance state.

5. The forming method according to claim 1 , wherein the breakdown operation is carried out with a laser of a power flux density comprised between 0.06 and 0.12 W/μm 2 .

6. The forming method according to claim 1 , wherein the breakdown operation is carried out with a laser beam of a diameter greater than three times the width and/or the length of the memory cell.

7. The forming method according claim 1 , wherein the breakdown operation is carried out with a laser in which the pulses have a duration less than or equal to 1 μs.

8. The forming method according to claim 1 , wherein the breakdown operation is carried out with a laser beam emitted in a wavelength of the infrared or the ultraviolet.

9. A non-volatile memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode, wherein the layer of insulating material is made active by a forming method according to claim 1 such that said layer of insulating material is capable, after forming, to switch in a reversible manner between a high resistance state and a low resistance state.

10. The non-volatile memory cell according to claim 9 , wherein the upper electrode is made of titanium, the lower electrode is made of titanium nitride and the layer of insulating material is made of hafnium oxide.

11. The non-volatile memory cell according to claim 9 , comprising a selection device, connected to the stack of the lower electrode, the layer of insulating material and the upper electrode, to control the current flowing in said stack.

12. A microelectronic device comprising a plurality of memory cells according to claim 9 , laid out beside each other.

13. The microelectronic device according to claim 12 , wherein the memory cells are laid out in a crossbar type architecture.

Assignees

• Commissariat Energie Atomique
• Univ Aix Marseille
• Centre Nat Rech Scient

Inventors

• Krakovinsky Alexis
• Bocquet Marc
• Coignus Jean
• Della Marca Vincenzo
• Portal Jean-Michel
• Wacquez Romain

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G11C7/005

  with combined beam-and individual cell access · CPC title

• H01L27/2463

  Electricity · mapped topic

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C2213/52

  Structure characterized by the electrode material, shape, etc. · CPC title