Electronic device and method for fabricating the same
US-2016071905-A1 · Mar 10, 2016 · US
Semiconductor memory device with variable resistance elements
US10355203B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10355203-B2 |
| Application number | US-201615261828-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 9, 2016 |
| Priority date | Mar 14, 2016 |
| Publication date | Jul 16, 2019 |
| Grant date | Jul 16, 2019 |
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Abstract
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In general, according to one embodiment, a semiconductor memory device includes: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; and a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer; a first transistor including first and second diffusion layers provided in the semiconductor layer, a gate insulation film, and a gate electrode; a first plug coupling the first diffusion layer and the first variable resistance element; and a second plug coupling the second diffusion layer and the first interconnect, wherein a portion of a side surface of the second plug is in contact with the first interconnect. 2. The device according to claim 1 , wherein: each of the first and second variable resistance elements is a magnetic tunnel junction (MTJ) element, the MTJ element includes a magnesium oxide (MgO) layer, and a level of a bottom surface of the MgO layer is between levels of a bottom surface and a top surface of the first interconnect. 3. A semiconductor memory device comprising: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer; a first transistor including first and second diffusion layers provided in the semiconductor layer, a gate insulation film, and a gate electrode; a first plug coupling the first diffusion layer and the first variable resistance element; a second plug coupling the second diffusion layer and the first interconnect; third and fourth plugs coupled to the first and second variable resistance elements, respectively; and second and third interconnects extending in the first direction and provided on the third and fourth plugs, respectively, wherein a level of a bottom surface of the first interconnect differs from levels of bottom surfaces of the second and third interconnects. 4. The device according to claim 3 , wherein: each of the first and second variable resistance elements is a magnetic tunnel junction (MTJ) element, the MTJ element includes a magnesium oxide (MgO) layer, and a level of a bottom surface of the MgO layer is between levels of the bottom surface and a top surface of the first interconnect.
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Frequently asked questions
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- What does patent US10355203B2 cover?
- In general, according to one embodiment, a semiconductor memory device includes: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; and a first interconnect extending in a first direction and provided on the first insulation layer, at lea…
- Who is the assignee on this patent?
- Toshiba Memory Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 16 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).