Silicon epitaxial wafer and method of producing silicon epitaxial wafer

Patent metadata

Field	Value
Publication number	US-10355092-B2
Application number	US-201414785720-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	May 10, 2013
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×1016 to 2×1017 atoms/cm3, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer.

First claim

The invention claimed is:

1. A silicon epitaxial wafer comprising:
a silicon substrate doped with carbon, the silicon substrate being produced by being cut from a silicon single crystal ingot grown by a Czochralski method so as to have a carbon concentration ranging from 3×10 16 to 2×10 17 atoms/cm 3 ;
a first intermediate epitaxial layer that is doped with a dopant and disposed on the silicon substrate;
an epitaxial layer stacked on the first intermediate epitaxial layer, the epitaxial layer being a region at which a device is to be formed; and
a second intermediate epitaxial layer disposed between the silicon substrate and the first intermediate epitaxial layer, wherein
the second intermediate epitaxial layer has a thickness ranging from 0.5 μm to 2 μm,
the silicon substrate is an n-type silicon substrate,
the second intermediate epitaxial layer is an n − -type second intermediate epitaxial layer,
the first intermediate epitaxial layer is an n + -type first intermediate epitaxial layer,
the epitaxial layer of the device forming region is an n − -type epitaxial layer, and
a p/n boundary is formed by ion implanting of p-type elements into the epitaxial layer of the device forming region.

2. The silicon epitaxial wafer according to claim 1 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped, which thickness is decreased if the amount of carbon is too low or increased if the amount of carbon is too high.

3. The silicon epitaxial wafer according to claim 1 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on a position at which the silicon substrate is cut from the silicon single crystal ingot, and,
for a silicon substrate cut from the first half portion of the cone side in the single crystal growth direction, the second intermediate epitaxial layer has a first thickness, and
for a silicon substrate cut from the second half portion of the tail side, the second intermediate epitaxial layer has a second thickness that is thicker than the first thickness.

4. A method of producing a silicon epitaxial wafer, comprising:
preparing a silicon substrate that is doped with carbon and produced by cutting a silicon single crystal ingot grown by a Czochralski method so as to have a carbon concentration ranging from 3×10 16 to 2×10 17 atoms/cm 3 ;
forming a first intermediate epitaxial layer doped with a dopant over the silicon substrate;
stacking an epitaxial layer on the first intermediate epitaxial layer, the epitaxial layer being a region at which a device is to be formed; and
forming a second intermediate epitaxial layer on the silicon substrate before forming the first intermediate epitaxial layer, wherein
the second intermediate epitaxial layer is formed so as to have a thickness ranging from 0.5 μm to 2 μm,
the silicon substrate is an n-type silicon substrate,
the second intermediate epitaxial layer is an n − -type second intermediate epitaxial layer,
the first intermediate epitaxial layer is an n + -type first intermediate epitaxial layer,
the epitaxial layer of the device forming region is an n − -type epitaxial layer, and
a p/n boundary is formed by ion implanting of p-type elements into the epitaxial layer of the device forming region.

5. The method according to claim 4 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped, which thickness is decreased if the amount of carbon is too low or increased if the amount of carbon is too high.

6. The method according to claim 4 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on a position at which the silicon substrate is cut from the silicon single crystal ingot, and,
for a silicon substrate cut from the first half portion of the cone side in the single crystal growth direction, the second intermediate epitaxial layer has a first thickness, and
for a silicon substrate cut from the second half portion of the tail side, the second intermediate epitaxial layer has a second thickness that is thicker than the first thickness.

Assignees

• Shinetsu Handotai Kk

Inventors

• Sakurada Masahiro

Classifications

• H10P14/3441

  Conductivity type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P36/20

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10P14/3444

  P-type · CPC title