Electrostatic discharge (ESD) protection in an electronic switching circuit

Patent metadata

Field	Value
Publication number	US-10354994-B2
Application number	US-201615298430-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Mar 24, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Aspects disclosed herein include electrostatic discharge (ESD) protection in an electronic switching circuit. An electronic switching circuit includes switching circuitry configured to provide interconnectivity between a common port in at least one common branch and an input/output (I/O) port in at least one I/O branch. The common branch and the I/O branch each include a blocking capacitor element that is inherently incapable for ESD discharging. As such, an ESD clamp is disposed in parallel to the blocking capacitor element to provide a low-impedance ESD discharging path around the blocking capacitor element. By disposing the ESD clamp in parallel to the blocking capacitor element, it is possible to minimize detrimental parasitic effects of the ESD clamp, thus improving performance and reliability of the electronic switching circuit, especially for high power switching circuits such as a radio frequency (RF) switching circuits.

First claim

What is claimed is:

1. An electronic switching circuit comprising:
switching circuitry;
at least one common branch comprising a first blocking capacitor element provided between a common port and the switching circuitry;
at least one input/output (I/O) branch comprising a second blocking capacitor element provided between the switching circuitry and an I/O port;
a common branch electrostatic discharge (ESD) clamp disposed in parallel to the first blocking capacitor element for discharging an ESD event around the first blocking capacitor element; and
an I/O branch ESD clamp disposed in parallel to the second blocking capacitor element for discharging the ESD event around the second blocking capacitor element.

2. The electronic switching circuit of claim 1 further comprising:
at least one shunt branch comprising a third blocking capacitor element provided between the switching circuitry and a ground rail; and
a shunt branch ESD clamp disposed in parallel to the third blocking capacitor element for discharging the ESD event around the third blocking capacitor element to the ground rail.

3. The electronic switching circuit of claim 2 wherein:
the switching circuitry is configured to couple the common branch ESD clamp to the shunt branch ESD clamp when the ESD event occurs at the common port in the at least one common branch; and
the common branch ESD clamp is configured to discharge the ESD event from the common port to the ground rail via the shunt branch ESD clamp.

4. The electronic switching circuit of claim 2 wherein:
the switching circuitry is configured to couple the I/O branch ESD clamp to the shunt branch ESD clamp when the ESD event occurs at the I/O port in the at least one I/O branch; and
the I/O branch ESD clamp is configured to discharge the ESD event from the I/O port to the ground rail via the shunt branch ESD clamp.

5. The electronic switching circuit of claim 2 wherein:
the switching circuitry is configured to couple the common branch ESD clamp and the I/O branch ESD clamp to the shunt branch ESD clamp when the ESD event occurs at the common port in the at least one common branch and at the I/O port in the at least one I/O branch;
the common branch ESD clamp is configured to discharge the ESD event from the common port to the ground rail via the shunt branch ESD clamp; and
the I/O branch ESD clamp is configured to discharge the ESD event from the I/O port to the ground rail via the shunt branch ESD clamp.

6. The electronic switching circuit of claim 2 wherein the common branch ESD clamp is configured to discharge the ESD event around the first blocking capacitor element in response to a first positive voltage spike placed between the common port and the ground rail being higher than a first positive trigger voltage of the common branch ESD clamp.

7. The electronic switching circuit of claim 2 wherein the I/O branch ESD clamp is configured to discharge the ESD event around the second blocking capacitor element in response to a second positive voltage spike placed between the I/O port and the ground rail being higher than a second positive trigger voltage of the I/O branch ESD clamp.

8. The electronic switching circuit of claim 2 wherein:
the common branch ESD clamp is configured to discharge the ESD event around the first blocking capacitor element in response to a first positive voltage spike placed between the common port and the ground rail being higher than a first positive trigger voltage of the common branch ESD clamp; and
the I/O branch ESD clamp is configured to discharge the ESD event around the second blocking capacitor element in response to a second positive voltage spike placed between the I/O port and the ground rail being higher than a second positive trigger voltage of the I/O branch ESD clamp.

9. The electronic switching circuit of claim 2 wherein the common branch ESD clamp is configured to discharge the ESD event around the first blocking capacitor element in response to a first negative voltage spike placed between the common port and the ground rail being lower than a first negative trigger voltage of the common branch ESD clamp.

10. The electronic switching circuit of claim 2 wherein the I/O branch ESD clamp is configured to discharge the ESD event around the second blocking capacitor element in response to a second negative voltage spike placed between the I/O port and the ground rail being lower than a second negative trigger voltage of the I/O branch ESD clamp.

11. The electronic switching circuit of claim 2 wherein:
the common branch ESD clamp is configured to discharge the ESD event around the first blocking capacitor element in response to a first negative voltage spike placed between the common port and the ground rail being lower than a first negative trigger voltage of the common branch ESD clamp; and
the I/O branch ESD clamp is configured to discharge the ESD event around the second blocking capacitor element in response to a second negative voltage spike placed between the I/O port and the ground rail being lower than a second negative trigger voltage of the I/O branch ESD clamp.

12. The electronic switching circuit of claim 2 wherein the common branch ESD clamp comprises:
a first trigger resistor comprising a first gate end and a first source end;
a second trigger resistor comprising a second gate end and a second source end;
a first transistor comprising a first drain electrode, a first gate electrode, and a first source electrode, wherein:
the first drain electrode is coupled to the common port;
the first gate electrode is coupled to the first gate end of the first trigger resistor; and
the first source electrode is coupled to the first source end of the first trigger resistor and the second source end of the second trigger resistor; and

a second transistor comprising a second drain electrode, a second gate electrode, and a second source electrode, wherein:
the second drain electrode is coupled to the switching circuitry;
the second gate electrode is coupled to the second gate end of the second trigger resistor; and
the second source electrode is coupled to the first source electrode of the first transistor.

13. The electronic switching circuit of claim 12 wherein:
the first transistor is substantially identical to the second transistor; and
the first trigger resistor and the second trigger resistor have a substantially equal resistance.

14. The electronic switching circuit of claim 2 wherein the I/O branch ESD clamp comprises:
a first trigger resistor comprising a first gate end and a first source end;
a second trigger resistor comprising a second gate end and a second source end;
a first transistor comprising a first drain electrode, a first gate electrode, and a first source electrode, wherein:
the first drain electrode is coupled to the I/O port;
the first gate electrode is coupled to the first gate end of the first trigger resistor; and
the first source electrode is coupled to the first source end of the first trigger resistor and the second source end of the second trigger resistor; and

a second transistor comprising a second drain electrode, a second gate electrode, and a second source electrode, wherein:
the second drain electrode is coupled to the switching circuitry;
the second gate electrode is coupled to the second gate end of the second trigger resistor; and
the second source electrode is coupled to the first source electrode of the first transistor.

15. The electronic switching circuit of claim 14 wherein:
the first transistor is substantially identical to the second transistor;

Assignees

• Qorvo Us Inc

Inventors

• Robbins David
• Muthukrishnan Swaminathan

Classifications

• H01L27/0288

  Electricity · mapped topic

• H01L27/0285 Primary

  Electricity · mapped topic

• H01L27/0292

  Electricity · mapped topic

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/921 Primary

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title