Semiconductor device

Patent metadata

Field	Value
Publication number	US-10354953-B2
Application number	US-201815994284-A
Country	US
Kind code	B2
Filing date	May 31, 2018
Priority date	Mar 26, 2015
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a first impurity region in a first region of a semiconductor substrate;
forming a second impurity region in a second region of the semiconductor substrate;
forming a first channel region by an epitaxial growth above the first impurity region;
forming an isolation film that separates the first region and the second region in the semiconductor substrate;
forming a first gate insulating film above the first region;
forming a second gate insulating film above the second region;
forming a gate electrode film above the first gate insulating film and the second gate insulating film;
forming a first gate electrode of the gate electrode film above the first region remaining the gate electrode film above the second region;
forming a first sidewall insulating film on a sidewall of the first gate electrode and above the first region;
forming a second gate electrode of the gate electrode film above the second region;
forming a second sidewall insulating film on a sidewall of the second gate electrode and above the second region;
forming a first source region and a first drain region on both sides of the first gate electrode above the first region; and
forming a second source region and a second drain region on both sides of the second gate electrode above the second region,
wherein:
a first transistor includes the first impurity region, the first channel region, the first gate insulating film, the first gate electrode, the first sidewall insulating film, the first source region and the first drain region;
a second transistor includes the second impurity region, the second gate insulating film, the second gate electrode, the second sidewall insulating film, the second source region and the second drain region;
the first transistor stores information by accumulating charge in the first sidewall insulating film;
the first impurity region includes a first impurity and a second impurity, the second impurity suppresses a diffusion of the first impurity, the first impurity includes at least Boron and the second impurity includes at least Germanium and Carbon; and
a thickness of the first gate insulating film is larger than a thickness of the second gate insulating film.

2. The method according to claim 1 , wherein an impurity concentration of the first impurity region is more than 1×10 18 cm −3 .

3. The method according to claim 1 , further comprising:
forming a third impurity region on an inner side of the first source region and the first drain region below the first sidewall insulating film,
wherein:
an impurity concentration of the third impurity region is lower than an impurity concentration of the first source region and the first drain region and is lower than an impurity concentration of the first impurity region.

4. The method according to claim 3 , wherein:
the first source region and the first drain region contain a third impurity of a first conductivity type;
the third impurity region contains a fourth impurity of the first conductivity type; and
the first impurity region contains a fifth impurity of a second conductivity type different from the first conductivity type.

5. The method according to claim 3 , wherein the impurity concentration of the third impurity region is equal to or less than 5×10 17 cm −3 .

6. The method according to claim 3 , wherein the impurity concentration of the first impurity region is more than 1×10 18 cm −3 .

7. The method according to claim 3 , further comprising:
forming a fourth impurity region on an inner side of the second source region and the second drain region below the second sidewall insulating film,
wherein:
an impurity concentration of the fourth impurity region is lower than an impurity concentration of the second source region and the second drain region; and
the impurity concentration of the third impurity region is equal to or less than one tenth of the impurity concentration of the fourth impurity region.

8. The method according to claim 3 , wherein the first impurity region contacts the third impurity region.

9. The method according to claim 1 , further comprising:
forming a fifth impurity region below the first impurity region of the semiconductor substrate,
wherein an impurity concentration of the fifth impurity region is higher than an impurity concentration of the first channel region.

10. The method according to claim 1 , wherein an impurity concentration of the first channel region is equal to or less than 1×10 17 cm −3 .

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Ema Taiji
• Yasuda Makoto
• Mizutani Kazuhiro

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L21/823493

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic