Insulator structure for avoiding abnormal electrical discharge and plasma concentration

US10354844B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10354844-B2
Application numberUS-201715594445-A
CountryUS
Kind codeB2
Filing dateMay 12, 2017
Priority dateMay 12, 2017
Publication dateJul 16, 2019
Grant dateJul 16, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An insulator for a processing apparatus including an upper electrode, a lower electrode and a reaction chamber, the insulator being adapted to be arranged around the upper electrode and the insulator including: a bottom end adapted to face the reaction chamber; and a side wall facing a side wall of the upper electrode, wherein an edge portion of the bottom end of the insulator extends radially inwardly to form a projecting portion such that the projecting portion covers an edge of a bottom surface of the upper electrode and a clearance between the side wall of the upper electrode and the side wall of the insulator.

First claim

Opening claim text (preview).

What is claimed is: 1. An insulator adapted to be installed in a plasma deposition or plasma etching apparatus, the plasma deposition or plasma etching apparatus comprising an upper electrode, a lower electrode and a reaction chamber, the insulator adapted to be arranged around the upper electrode and comprising: a bottom end portion adapted to face the reaction chamber; and a side wall configured to face a side wall of the upper electrode, the side wall of the upper electrode being at an angle to a bottom surface of the upper electrode, wherein an edge portion of the bottom end portion of the insulator is arranged to extend inwardly toward a center part of the bottom surface of the upper electrode to form a projecting portion, wherein at least part of the projecting portion is arranged to be located vertically underneath at least part of the upper electrode, and wherein a portion of a surface, arranged to face upward toward the upper electrode, of the insulator is configured to form an open gap located vertically above the portion of the surface of the insulator, the open gap located between the upper electrode and the portion of the surface of the insulator. 2. The insulator of claim 1 , wherein the projecting portion has a thickness selected from the range of about 0.5 to about 2.0 millimeters. 3. The insulator of claim 1 , wherein, when the insulator is installed, a distance between the bottom surface of the upper electrode and a top end surface of the projecting portion is selected from the range of about 0.1 to about 1.0 millimeter. 4. The insulator of claim 1 , wherein, when the insulator is installed, the position of a bottom surface of the projecting portion is selected from the range of about 0.6 to about 2.9 millimeters below the position of the bottom surface of the upper electrode in a direction perpendicular to the bottom surface of the upper electrode. 5. The insulator of claim 1 , wherein, when the insulator is installed, the position of a bottom surface of the projecting portion is about 1.2 millimeters below the position of the bottom surface of the upper electrode in a direction perpendicular to the bottom surface of the upper electrode. 6. The insulator of claim 1 , wherein the projecting portion projects about 5-25 millimeters inwardly such that the projecting portion covers the edge of the bottom surface of the upper electrode. 7. A substrate processing apparatus comprising the insulator of claim 1 . 8. The substrate processing apparatus of claim 7 , wherein the edge of the bottom surface of the upper electrode is rounded or chamfered. 9. The substrate processing apparatus of claim 7 , wherein the edge of the bottom surface of the upper electrode is rounded or chamfered with a radius being the same as or more than the thickness of a sheath area generated within the reaction chamber. 10. The substrate processing apparatus of claim 7 , wherein the edge of the bottom surface of the upper electrode is rounded or chamfered with a radius selected from the range of about 0.05 to about 10 millimeters. 11. The substrate processing apparatus of claim 7 , wherein the edge of the bottom surface of the upper electrode is rounded or chamfered with a radius of about 5 millimeters. 12. A processing apparatus comprising: an upper electrode having a side wall and a bottom surface, the side wall being at an angle to the bottom surface; a lower electrode; a workpiece support; a reaction chamber; and an insulator arranged around the upper electrode, the insulator comprising: a bottom end portion adapted to face the reaction chamber, and a side wall facing the side wall of the upper electrode, wherein an edge portion of the bottom end portion of the insulator extends inwardly toward a center part of the bottom surface of the upper electrode to form a projecting portion protruding from the bottom end portion, at least part of the projecting portion located vertically underneath the upper electrode, and wherein an open gap is located vertically above a portion of a surface, facing upward toward the upper electrode, of the insulator, the open gap located between the upper electrode and the portion of the surface of the insulator. 13. The processing apparatus of claim 12 , wherein the position of a bottom surface of the projecting portion is selected from the range of about 0.6 to about 2.9 millimeters below the position of the bottom surface of the upper electrode in a direction perpendicular to the bottom surface of the upper electrode. 14. The processing apparatus of claim 12 , wherein the position of a bottom surface of the projecting portion is about 1.2 millimeters below the position of the bottom surface of the upper electrode in a direction perpendicular to the bottom surface of the upper electrode. 15. The processing apparatus of claim 12 , wherein the processing apparatus is configured for deposition or etching of a material on a workpiece. 16. The processing apparatus of claim 12 , wherein the projecting portion has a thickness selected from the range of about 0.5 to about 2.0 millimeters. 17. The processing apparatus of claim 12 , wherein a distance between the bottom surface of the upper electrode and a top end surface of the projecting portion is selected from the range of about 0.1 to about 1.0 millimeter. 18. The processing apparatus of claim 12 , wherein the position of a bottom surface of the projecting portion is selected from the range of about 0.6 to about 2.9 millimeters below the position of the bottom surface of the upper electrode in a direction perpendicular to the bottom surface of the upper electrode. 19. The processing apparatus of claim 12 , wherein the projecting portion projects about 5-25 millimeters inwardly such that the projecting portion covers the edge of the bottom surface of the upper electrode. 20. The processing apparatus of claim 12 , wherein the edge of the bottom surface of the upper electrode is rounded or chamfered with a radius selected from the range of about 0.05 to about 10 millimeters.

Assignees

Inventors

Classifications

  • Relative arrangement or disposition of electrodes; moving means · CPC title

  • Gas supply means · CPC title

  • CVD [Chemical Vapor Deposition] · CPC title

  • Etching · CPC title

  • Radio frequency generated discharge (H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence) · CPC title

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What does patent US10354844B2 cover?
An insulator for a processing apparatus including an upper electrode, a lower electrode and a reaction chamber, the insulator being adapted to be arranged around the upper electrode and the insulator including: a bottom end adapted to face the reaction chamber; and a side wall facing a side wall of the upper electrode, wherein an edge portion of the bottom end of the insulator extends radially …
Who is the assignee on this patent?
Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H01J37/32568. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 16 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).